Dynamically adjustable tapped delay line

Details Dynamically adjustable tapped delay line Dynamically adjustable tapped delay line

1999-09-27

2002-04-09

Pascal, Robert (Department: 2817)

Wave transmission lines and networks

Coupling networks

Delay lines including a lumped parameter

C333S166000

Reexamination Certificate

active

06369670

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to electronic circuits and, more particularly, to circuits using delay lines.
2. Description of the Related Art
In complex electronic circuits, it is not uncommon to for circuit designers to use one or more delay lines in order to adjust the relationship between signals such that multiple signals are aligned within a predetermined time window.
A problem with using delay lines to align signals concerns the multiple factors that have bearing on the amount of delay provided by the delay line. First, fabrication variations will cause delay lines from chip to chip to vary. Second, operating temperature, voltage and other environmental variations can affect the delay provided by the delay lines. Accordingly, a delay line having variations at one extreme can have a significantly greater delay than a delay line at the opposite extreme.
A circuit designer can ameliorate some variations by careful design. Commonly, delay lines are designed such that the delayed signals will be aligned at the middle of a time window under nominal conditions to provide as much leeway on either side of nominal as possible. Further, improved processing techniques can reduce variations between chips. However, as circuits are designed to operate at higher and higher speeds, the tolerance for variations is greatly reduced and the precautions described above have less chance of success.
Accordingly, a need has arisen for a highly accurate delay line.
BRIEF SUMMARY OF THE INVENTION
A circuit generates one or more signals to be delayed. Tapped delay lines are coupled to the signals, each tapped delay line including a plurality of delay elements and having a plurality of exit points through which said signal may propagate. A test circuit determines a delay associated with a delay element in the circuit and selects one of said exit points of each of said tapped delay lines based on said delay.
The present invention provides significant advantages over the prior art. First, a high degree of accuracy can be maintained in delaying signals to align within a given time window by using actual data during operation of the circuit. Second, the accuracy can be maintained despite changing environmental conditions. Third, the addition of the test circuitry adds only a minimal amount of additional devices to a circuit.


REFERENCES:
patent: 5663767 (1997-09-01), Rumreich et al.
patent: 5900762 (1999-05-01), Ramakrishnan

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