Dynamically adjustable slurry feed arm for wafer edge...

Details Dynamically adjustable slurry feed arm for wafer edge... Dynamically adjustable slurry feed arm for wafer edge...

2003-02-20

2004-11-23

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C438S693000, C451S005000, C451S008000

Reexamination Certificate

active

06821895

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to chemical mechanical polishing (CMP) and more particularly to a dynamically adjustable slurry feed arm and method for adjusting the same for improving a polishing layer thickness uniformity including a process surface wafer edge profile in a CMP process.
BACKGROUND OF THE INVENTION
In semiconductor fabrication integrated circuits and semiconducting devices are formed by sequentially forming features in sequential layers of material in a bottom-up manufacturing method. The manufacturing process utilizes a wide variety of deposition techniques to form the various layered features including various etching techniques such as anisotropic plasma etching to form device feature openings followed by deposition techniques to fill the device features. In order to form reliable devices, close tolerances are required in forming features including anisotropic etching techniques which rely heavily on layer planarization to form consistently deep anisotropically etched features.
In addition, excessive degrees of surface nonplanarity will undesirably affect the quality of several semiconductor manufacturing processes including, for example, photolithographic patterning processes, where the positioning the image plane of the process surface within an increasingly limited depth of focus window is required to achieve high resolution semiconductor feature patterns.
Chemical mechanical polishing (CMP) is increasingly being used as a planarizing process for semiconductor device layers, especially for devices having multi-level design and smaller semiconductor fabrication processes, for example, below about 0.25 micron. CMP planarization is typically used several different times in the manufacture of a multi-level semiconductor device, including planarizing levels of a device containing both dielectric and metal portions to achieve global planarization for subsequent processing of overlying levels.
For example, in the CMP of oxide containing layers such as dielectric insulating layers also referred to as inter-layer dielectric (ILD) layers and inter-metal dielectric (IMD) layers, it is important to achieve a high degree of planarity during ILD removal. For example, following formation of the ILD layer, via formation process is carried out to form electrical interconnections between electrically conductive portions of an underlying ILD layer and an electrically conductive portion of an overlying ILD layer. In the event that the thickness uniformity is not within specifications following the oxide or ILD CMP process, a subsequent anisotropic etching process in relatively thicker ILD layer portions to form the via interconnect, for example at a wafer edge portion (e.g., periphery) may not be sufficiently deep to make contact with the conductive portion of the underlying ILD layer, thus resulting in an open circuit in the integrated circuit semiconductor device. On the other hand, if the wafer edge portion is relatively overpolished resulting in a relatively thinner ILD layer portion, a subsequent via etching process can result in metal thinning in the underlying conductive region altering electrical resistances.
The well known Preston equation generally explains the polishing mechanism for dielectric layers, particularly SiO
2
containing dielectric layers. Generally the rate of removal is proportional to the applied pressure, the relative velocity between the wafer and the polishing pad and a proportionality constant that takes into account other variables such as the hardness of the dielectric, the slurry, and the polishing pad.
One process that is as yet not quantitatively understood is the role of the slurry in forming a hydrodynamic layer underneath the wafer polishing surface during CMP. The distribution of the slurry with respect to the polishing surface has received little attention in the prior art. For example, it is known that both mechanical and chemical processes account for polishing of the surface. For example, chemical processes are known to dominate on the micro scale in removing material while mechanical processes dominate on the macro scale, for example in removing high spots on the wafer surface. In addition, the condition of the polishing pad affects both chemical and mechanical processes.
Prior art processes have proposed feeding the slurry through the polishing pad to make the delivery of the slurry to the wafer polishing surface more uniform. This process has met with some success but has proved difficult to control with respect to varying polishing pad surfaces and the particular CMP machine used. For example, the edge of the wafer may tend to get a higher or lower supply of slurry due to the complex relative motion of the polishing pad and the wafer polishing surface which may be moved at varying rates relative to one another. Prior art approaches to compensate for this effect have included making the wafer holder surface (carrier) slightly convex to achieve higher polishing rates at the center portion of the wafer. This approach is highly dependent on the type of slurry, the nature of the polishing pads, and the CMP machine, making consistent results a sort of ‘black art’ based on trial and error approaches.
Therefore, there is a need in the semiconductor art to develop an improved CMP method and apparatus whereby the slurry may be selectively delivered to achieve consistently uniform polishing layer thicknesses by selectively delivering the slurry to predetermined areas of the polishing pad to compensate for differing material removal rates across the wafer surface.
It is therefore an object of the invention to provide an improved CMP method and apparatus whereby the slurry may be selectively delivered to achieve consistently uniform polishing layer thicknesses by selectively delivering the slurry to predetermined areas of the polishing pad to compensate for differing material removal rates across the wafer surface while overcoming other shortcomings and deficiencies in the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a dynamically adjustable slurry feed arm and method for adjusting the same in a CMP process.
In a first embodiment, the method includes carrying out the CMP process for a predetermined period of time on a substrate comprising a polishing layer to remove a portion of a polishing layer; determining the thickness of the polishing layer at a plurality of predetermined measurement areas comprising at least a polishing layer peripheral portion and a polishing layer center portion; determining a desired subsequent dispensing position to equalize the thickness of the polishing layer; and, adjusting the slurry feed arm to the subsequent dispensing position such that the slurry is dispensed over the polishing pad at the subsequent dispensing position comprising one of closer to the polishing pad center portion and closer to the polishing pad peripheral portion.
These and other embodiments and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.


REFERENCES:
patent: 6159075 (2000-12-01), Zhang
patent: 6303507 (2001-10-01), Wang et al.
patent: 6409579 (2002-06-01), White, II et al.

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