Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2007-01-09
2007-01-09
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S117000
Reexamination Certificate
active
10133685
ABSTRACT:
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time based on statistical thresholds or other selected criteria. Each map may include a series of locations on a wafer, the tests to perform at each location, and the measured results of each test. A parametric test system may perform the test at the associated location on the wafer. If the statistical threshold is exceeded or the selected criteria is met, the current map may be abandoned in favor of a different map.
REFERENCES:
patent: 4517512 (1985-05-01), Petrich et al.
patent: 4639664 (1987-01-01), Chiu et al.
patent: 4656632 (1987-04-01), Jackson
patent: 4985988 (1991-01-01), Littlebury
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5206582 (1993-04-01), Ekstedt et al.
patent: 5241266 (1993-08-01), Ahmad et al.
patent: 5326428 (1994-07-01), Farnworth et al.
patent: 5360747 (1994-11-01), Larson et al.
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5483175 (1996-01-01), Ahmad et al.
patent: 5491427 (1996-02-01), Ueno et al.
patent: 5523697 (1996-06-01), Farnworth et al.
patent: 5726920 (1998-03-01), Chen et al.
patent: 5736850 (1998-04-01), Legal
patent: 5787190 (1998-07-01), Peng et al.
patent: 5806181 (1998-09-01), Khandros et al.
patent: 5822717 (1998-10-01), Tsiang et al.
patent: 5845234 (1998-12-01), Testa et al.
patent: 5859964 (1999-01-01), Wang et al.
patent: 5869974 (1999-02-01), Akram et al.
patent: 5962862 (1999-10-01), Evers et al.
patent: 6031382 (2000-02-01), Nakaizumi
patent: 6113646 (2000-09-01), Holden
patent: 6119125 (2000-09-01), Gloudeman et al.
patent: 6208904 (2001-03-01), Mullen, Jr.
patent: 6210983 (2001-04-01), Atchison et al.
patent: 6240331 (2001-05-01), Yun
patent: 6304095 (2001-10-01), Miyamoto
patent: 6314034 (2001-11-01), Sugamori
patent: 6331783 (2001-12-01), Hauptman
patent: 6362013 (2002-03-01), Yoshimura
patent: 6370487 (2002-04-01), Dorough
patent: 6383825 (2002-05-01), Farnworth et al.
patent: 6420864 (2002-07-01), Abraham et al.
patent: 6445199 (2002-09-01), Satya et al.
patent: 6462575 (2002-10-01), Cram
patent: 6466314 (2002-10-01), Lehman
patent: 6486492 (2002-11-01), Su
patent: 6505138 (2003-01-01), Leonard
patent: 6507800 (2003-01-01), Sheu
patent: 6536006 (2003-03-01), Sugamori
patent: 6549863 (2003-04-01), Morinaga
patent: 6556938 (2003-04-01), Rohrbaugh et al.
patent: 6563331 (2003-05-01), Maeng
patent: 6567770 (2003-05-01), Dorough
patent: 6590408 (2003-07-01), Cheng et al.
patent: 6618682 (2003-09-01), Bulaga et al.
patent: 6624653 (2003-09-01), Cram
patent: 6625556 (2003-09-01), Conboy et al.
patent: 6629282 (2003-09-01), Sugamori et al.
patent: 6639417 (2003-10-01), Takao
patent: 6785413 (2004-08-01), Barcomb et al.
patent: 6859760 (2005-02-01), Dorough
patent: 2002/0000826 (2002-01-01), Takao
patent: 2002/0121915 (2002-09-01), Montull et al.
patent: 2002/0152046 (2002-10-01), Velichko et al.
patent: 2003/0028343 (2003-02-01), Velichko et al.
patent: 2003/0200513 (2003-10-01), Bergman Reuter et al.
patent: 2003/0208340 (2003-11-01), Dorough
patent: 2003/0212469 (2003-11-01), Wang et al.
patent: 2004/0153979 (2004-08-01), Chang
patent: 2004/0210413 (2004-10-01), Dorough et al.
patent: 2005/0021273 (2005-01-01), Dorough et al.
“Integrating expert systems with a relational database in semiconductor manufacturing”; Perez, R.A.; Koh, S.W.; IEEE Transactions on Semiconductor Manufacturing; vol. 6 Issue; Aug. 3, 1993; pp. 199-206.
“Standardization of CMOS unit process development”; Weber, C.; Proceedings 1989 International Conference on Microlectronic Test Structures; Mar. 13-14, 1989; pp. 39-44.
“The INMOS integrated parametric test and analysis system”; Cheung, D.; Clark, A.; Starr, R.; Proceedings 1989 International Conference on Microelectronic Test Structures; Mar. 13-14, 1989; pp. 45-50.
“An expert system for process diagnosis [MOS product testing]”; Hamilton, A.; Shofield, R.; Proceedings 1989 International Conference on Microelectronic Test Structures; Mar. 13-14, 1989; pp. 55-57.
“System engineering considerations and methodology for effecting a cohesive functional/parametric testing strategy”; Granieri, M.N.; IEEE Automatic Testing Conference; Sep. 25-28, 1989; pp. 1-8.
“In search of the optimum test set—adaptive test methods for maximum defect coverage and lowest test cost”; Madge, R.; Benware, B.; Turakhia, R.; Daasch, R.; Schuermyer, C.; Ruffler, J.; Proceedings. International Test Conference; Oct. 26-28, 2004; Page(s.
Fukuda, E., et al., “Advanced Process Control System Description of an Easy-to-use Control System Incorporating Pluggable Modules”,IEEE Intn'l Symposium on Semiconductor Manufacturing Conference Proceedings,(Oct. 11-13, 1999),321-324.
Blunn, R G., “Concurrent fault tolerant control of semiconductor measurement and testing”,2001 IEEE International Semiconductor Manufacturing Symposium,303.855us1,(Oct. 8-10, 2001),455-458.
Dorough, Michael J., et al., “Dynamic Adaptable Semiconductor Testing”,IEEE Proceedings of the 2002 International Symposium on Semiconductor Manufacturing, ISSM Catalog,(2002), 1-4.
Sedgewick, R.,Algorithms,Second Edition, Addison-Wesley Publishing Company, Inc.,(1988),pp. 516-519.
Blunn Robert G.
Dorough Michael J.
Velichko Sergey A.
Barlow John
Micro)n Technology, Inc.
Washburn Douglas N.
LandOfFree
Dynamically adaptable semiconductor parametric testing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamically adaptable semiconductor parametric testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamically adaptable semiconductor parametric testing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3727872