Dynamic write process for high bandwidth multi-bit-per-cell and

Details Dynamic write process for high bandwidth multi-bit-per-cell and Dynamic write process for high bandwidth multi-bit-per-cell and

1998-12-31

2000-10-17

Nelms, David

Static information storage and retrieval

Floating gate

Multiple values

36518522, 36518525, G11C 1134

Patent

active

06134141&

ABSTRACT:
A write process and circuit for a non-volatile memory such as a multi-bit-per-cell Flash memory has multiple local memory arrays and a global bias circuit that charges row lines in the arrays for programming operations. A programming operation in an array includes a charging period during which the global bias circuit charges a selected row line to a voltage corresponding to a value to be written in a memory cell and a sequence of program cycles and verify cycles during which the selected row line is isolated to preserve the charge from the bias circuit. A global control circuit can use a capacitive coupling to the charged row line to raise and lower the row line voltage. In one embodiment, the row line voltage rises to a programming voltage to change the threshold voltage of the selected cell during program cycles and falls to a verify voltage during verify cycles to sense whether the selected cell has a target threshold voltage. Alternatively, the row line voltage remains constant as charged by the bias circuit if a maximum current for biasing a column line connected to a sense amplifier causes the programming voltage to be equal to the trip point of the sense amplifier when the memory cell has the target threshold voltage.

REFERENCES:
patent: 5587951 (1996-12-01), Jazayeri et al.
patent: 5784315 (1998-07-01), Itoh

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