Dynamic type semiconductor memory device

Details Dynamic type semiconductor memory device Dynamic type semiconductor memory device

1990-07-24

1991-10-29

Hille, Rolf

Static information storage and retrieval

Interconnection arrangements

Magnetic

365210, 357 45, 357 68, G11C 508, G11C 702, H01L 2710, H01L 2348

Patent

active

050620770

ABSTRACT:
A dynamic-type semiconductor memory device comprises bit lines, every two bit lines forming a folded bit line pair, every two pairs forming a bit-line unit such that one of the bit lines of the first pair extends between the bit lines of the second pair, and the bit lines of the second pair are twisted at middle portion, word lines intersecting with the bit lines, dummy word lines, extending parallel to the word lines, two of the dummy word lines being arranged on one side of the crossing portions of the bit lines of the second pair, and the other two of the dummy word lines being arranged on the other side of the crossing portions of the bit lines of the second pair, memory cells connected to selected ones of the intersections of the bit lines and the word lines, such that any adjacent memory cells connected to the same word line form a group which is arranged every two bit lines, and any adjacent two memory cells connected to the same bit line are shifted by half-pitch distance with respect to the corresponding two adjacent memory cells connected to either adjacent bit line, a plurality of dummy cells connected to selected ones of the intersections of the bit lines and the word lines, such that at least one dummy cell is connected to each bit line, and sense amplifiers provided for the pairs of bit lines, respectively.

REFERENCES:
patent: 4044340 (1977-08-01), Itoh
patent: 4675845 (1987-06-01), Itoh et al.
patent: 4914502 (1990-04-01), Lebowitz et al.
patent: 4941031 (1990-07-01), Kumagai et al.
patent: 5014110 (1991-05-01), Satoh
"A 60-ns 3.3-V-Only 16-Mbit DRAM with Multipurpose Register", IEEE Journal of Solid-State CIrcuits, vol. 24, No. 5, Oct. 1989, Kazutami Arimoto et al., pp. 1184-1190.
Hidaka et al., "Twisted Bit-Line Architectures for Multi-Megabit DRAM's", IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 21-27.
Kumanoya et al., "A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, pp. 909-913.

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