Dynamic TTL input comparator for CMOS devices

Details Dynamic TTL input comparator for CMOS devices Dynamic TTL input comparator for CMOS devices

1981-10-02

1984-11-27

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307362, 307530, 307279, H03K 19094, H03K 524, H03K 3356, G01R 19165

Patent

active

044853173

ABSTRACT:
A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "0" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with an input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

REFERENCES:
patent: 3938109 (1976-02-01), Gionis et al.
patent: 3959781 (1976-05-01), Mehta et al.
patent: 4096402 (1978-06-01), Schroeder et al.
patent: 4110639 (1978-08-01), Redwine
patent: 4380710 (1983-04-01), Cohen et al.

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