Pulse or digital communications – Synchronizers
Reexamination Certificate
1998-05-27
2001-06-19
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
C375S317000, C327S067000, C327S087000
Reexamination Certificate
active
06249556
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to circuit design. In particular, the invention relates to dynamic thresholding for input receivers.
2. Description of Related Art
As speed of microprocessors becomes faster to meet the demanding needs in the technology, the design of transmission and interconnection lines becomes more and more critical. Data integrity and reliable signal detection at the transmitting and receiving ends are important to ensure performance at high speeds.
When signal lines are combined together to form a signal bus, signal transmission and reception are sensitive to noise and crosstalk. The signals on these buses usually have fast edge rates, in the order of 2 Volts
anosecond (V
sec), or greater. Noise problems are caused by parasitic capacitance of the load and the unavoidable addition of stubs, normally the wire connections at a bus generated by the packaging design.
Stubs and parasitic capacitance are the two main sources that generate signal reflections that manifest themselves as undershoot and overshoot which lead to ringback. As clock speeds increase, these ringbacks may result in incorrect signal detection.
Signal detection in digital circuits usually uses a thresholding scheme. In this scheme, the signal to be detected is compared with a threshold voltage. This threshold voltage is usually a reference voltage, V
REF
, which is fixed at a constant value. In positive logic detection, if the signal level is above V
REF
, it is declared a logic one; otherwise, it is declared a logic zero.
The thresholding scheme works reasonably well for medium clock speeds. As clock speeds increase, the ringbacks caused by the overshoots and undershoots may result in incorrect thresholding, leading to erroneous signal detection.
There are a number of techniques in the prior art to deal with the problem. One technique imposes rigid rules in the routing of signal lines. The high speed signal lines are required to run at short distances to avoid stray capacitance and other crosstalk effects. The disadvantages of this technique include difficulties in signal routing, component placement, and board density allocation. Another technique is the use of hysterisis as in the Schmitt trigger. Although the Schmitt trigger technique provides some tolerance to the ringback portion of the signal, it causes extra delay in recognizing the signal transition.
Therefore there is a need in the technology to provide an efficient and reliable thresholding scheme for the input receivers that can operate at high speeds.
SUMMARY OF THE INVENTION
The present invention discloses a method and apparatus for thresholding an input signal synchronous with a clock signal at a receiver. Briefly, in one embodiment, the input signal is compared with a threshold voltage to produce a difference signal. The difference signal is synchronized with the input signal to generate a feedback signal. The threshold voltage is adjusted based on the feedback signal.
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patent: 6094461 (2000-07-01), Heron
Hampton, III Harry L.
Rees Roger R.
Al-Beshrawi Tony
Blakely , Sokoloff, Taylor & Zafman LLP
Chin Stephen
Intel Corporation
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