Dynamic threshold voltage scheme for low voltage CMOS inverter

Details Dynamic threshold voltage scheme for low voltage CMOS inverter Dynamic threshold voltage scheme for low voltage CMOS inverter

1995-11-13

1997-07-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327389, 327391, 327387, 326 27, 326108, H03K 19003, H03K 190185

Patent

active

056442661

ABSTRACT:
The present invention utilizes a CMOS (complementary metal-oxide-semiconductor) inverter, which includes a PMOS transistor and an NMOS transistor connected in cascade, and back-gate biasing circuits. The back-gate biasing circuit consists of capacitors and loads (active load or passive load). By providing a bias voltage to either one of bulks of the transistors or both of them, the constituted CMOS inverter demonstrates higher operation speed and lower standby current than the conventional one.

REFERENCES:
patent: 4947056 (1990-08-01), Jinbo
patent: 5212415 (1993-05-01), Murakami et al.
patent: 5381056 (1995-01-01), Murphy
patent: 5461265 (1995-10-01), Kunihisa et al.
patent: 5543734 (1996-08-01), Volk et al.

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