Dynamic threshold source follower voltage driver circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S170000, C327S112000

Reexamination Certificate

active

06271713

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to circuits and more particularly, to a dynamic threshold source follower voltage driver circuit.
2. Background Art
A driver circuit is used to provide the ability to quickly change the input voltage of a receiver circuit that it drives. Instances in which a driving circuit may be used include to drive a relatively long interconnect conductor and to drive a wide fan-out set of conductors. A commonly used driver circuit includes first and second inverters connected in series, wherein each inverter includes a pull-up p-channel metal oxide semiconductor field effect transistor (pMOSFET) in series with a pull down n-channel MOSFET (nMOSFET). The input to the driver is the input to the first inverter. The output of the first inverter is the input to the second inverter and the output of the second inverter is the output of the driver.
Point-to-point on-chip interconnects between and within microprocessor datapath Functional Unit Blocks (FUBs) have evolved with integration as major on-chip performance and power bottlenecks. A reason for this is that interconnect capacitance per unit length, dominated by sidewall fringing and cross-coupling, may increase hyperbolically with lateral dimension scaling and hence scale slower than gate capacitance does, despite technology enhancements such as low-K dielectric materials and copper metallization.
Dynamic threshold (Vt) based circuit techniques have been investigated for low-voltage datapath circuits and interconnect drivers. See, e.g., F. Assaderaghi et al., “A Dynamic Threshold Voltage MOS (DTMOS) for Very Low Voltage Operation,” IEEE Electron Device Letters, December 1994, pp. 510-512; and U.S. Pat. No. 5,559,368. These circuits possess “dynamic” Vt transistors, i.e., transistors whose Vt changes as the gate switches. Therefore, as the input transitions, the gate-to-bulk forward bias voltage of the switching transistor increases, causing a Vt reduction (due to body effect) as the gate switches. However, since the bulk terminals are directly tied to the inputs, the fan-in gate capacitance is now substantially higher. This significantly degrades the potential performance benefits and may contribute to higher switched capacitance, and hence higher switching power consumption. Further, since each transistor must have its gate and bulk connected, a separate well is required for each device, resulting in considerable layout area penalties.
SUMMARY OF THE INVENTION
In some embodiments, the invention includes a die having a driver circuit. The driver circuit includes a driver input node and a driver output node. An nFET pull-up transistor is connected to the driver output node, and wherein the nFET pull-up transistor is at times forward body biased and the forward body bias is substantially greatest when a signal at the driver input node begins to switch high and substantially least when the switching has already essentially occurred.
In some embodiments, the driver includes a first inverter to receive an input signal from the driver input node and provide an inverted input signal at a first inverter output node. The driver includes second inverter to receive the inverted input signal from the first inverter output node and provide a driver output signal at the driver output node. The driver includes an nFET pull-up transistor connected between the driver output node and a power supply node, the nFET pull-up transistor having a gate tied to the driver input node.
In some embodiments, the nFET pull-up transistor is at times forward body biased.
Other embodiments are described and claimed.


REFERENCES:
patent: 4616148 (1986-10-01), Ochii et al.
patent: 4885479 (1989-12-01), Oritani
patent: 5034623 (1991-07-01), McAdams
patent: 5086427 (1992-02-01), Wittaker et al.
patent: 5434526 (1995-07-01), Tanigashira et al.
patent: 5461338 (1995-10-01), Hirayama et al.
patent: 5483181 (1996-01-01), D'Souza
patent: 5559368 (1996-09-01), Hu et al.
patent: 5559461 (1996-09-01), Yamashina et al.
patent: 5568062 (1996-10-01), Kaplinsky
patent: 5594361 (1997-01-01), Campbell
patent: 5604450 (1997-02-01), Borkar et al.
patent: 5644255 (1997-07-01), Taylor
patent: 5814899 (1998-09-01), Okumura
patent: 5852373 (1998-12-01), Chu et al.
patent: 5892372 (1999-04-01), Ciraula et al.
patent: 5917365 (1999-06-01), Houston
patent: 5986473 (1999-11-01), Krishnamurthy et al.
patent: 5994918 (1999-11-01), Mehra
patent: 6002292 (1999-12-01), Allen et al.
patent: 6044020 (2000-03-01), Chung et al.
P. Larsson et al., “Noise in Digital Dynamic CMOS Circuits,” IEE Journal of Solid-State Circuits, vol. 29, No. 6, Jun. 1994, pp. 655-662.
K. Shepard et al., “Noise in Deep Submicron Digital Design,” ICCAD '96, pp. 524-531, 1996.
Z. Wang et al., “Fast Adders Using Enhanced Multiple-Output Domino Logic,” IEEE Journal of Solid-State Circuits, vol. 32, No. 2, Feb. 1997, pp. 206-214.
PCT Published Application WO 98/59419.
U.S. Patent application, Ser. No. 09/157,089, filed Sep. 18, 1998.
J. Gil et al. “A High Speed and Low Power SOI Inverter using Active Body-Bias,” Int'l Symposium on Lower Power Electronics and Design, 1998, pp. 59-63.
F. Assaderaghi et al. “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation, ” IEDM 94, pp. 809-812, 1994.
F. Assaderaghi et al. “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Votlage Operation,” IEEE Electron Device Letters, vol. 15, No. 12, Dec. 1994, pp. 510-512.
Y. Nakagome et al. “Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's” IEEE Journal of Solid-State Circuits, vol. 28, No. 4, Apr. 1993, pp. 414-419.
T. Sakurai et al. “Low-Power CMOS Design through Vth Control and Low-Swing Circuits” Proceedings of Int'l Symp. On Low Power Electronics and Design, Aug. 18, 1997, pp. 1-6.
H. Zhang et al. “Low-Swing Interconnect Interface Circuits,” Proceedings of Int'l Symp. On Low Power Electronics and Design, Aug. 10, 1998, pp. 161-166.
M. Haycock et al., “A 2.5 Gb/s Bidirectional Signaling Technology,” Proceedings of IEEE Hot Interconnects Symposium, Aug. 21, 1997, pp. 149-156.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Dynamic threshold source follower voltage driver circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic threshold source follower voltage driver circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic threshold source follower voltage driver circuit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2489537

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.