Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1997-09-24
1999-11-02
Le, Thien
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
23546224, G06K 0710
Patent
active
059776633
ABSTRACT:
A threshold gate with registration embedded in the threshold logic is disclosed. A go-to-NULL network and a go to-data network receives data input having an asserted state and a NULL state. A directive or acknowledge signal is received by the embedded registrations network. The directive signal indicates whether an asserted state or the NULL state is desired at the output signal line. A data processing network is coupled to the go-to-NULL network to provide an output signal based upon the go-to-NULL network, the go-to-data network and the registration network. The go-to-data network provides a network of switches that cause an asserted state at the output signal line when a number of the data inputs in the asserted state exceeds a predetermined threshold and the acknowledge signal is in the asserted state. The go-to-NULL network provides a network of switches that cause a NULL state at the output signal line when all of the data inputs are in the NULL state and the acknowledge signal is in the NULL state. A reset network is included for providing system initialization at registration boundaries. The reset network is made transparent during normal operating conditions.
REFERENCES:
patent: 3449594 (1969-06-01), Gibson et al.
patent: 3519941 (1970-07-01), Winder
patent: 3715603 (1973-02-01), Lerch
patent: 4710650 (1987-12-01), Shorji
patent: 4845633 (1989-07-01), Furtek
patent: 5121003 (1992-06-01), Williams
patent: 5305463 (1994-04-01), Fant et al.
patent: 5382844 (1995-01-01), Knauer
Anantharaman, "A delay insensitive regular expression recognizer," research paper, Dept. of Computer Science, Carnegie-Mellon University, pp. 1-10 (Jan., 1989).
Brzozowski et al., "Asynchronous Circuits," Table of Contents, 20 pgs. (1995).
Burford et al., "An 180 Mhz 16 bit Multiplier Using Asynchronous Logic Design Techniques," IEEE 1994 Custom Integrated Circuits Conference, pp. 215-218 (1994).
Dean, "Strip: A Self-Timed Risk Processor," Dissertation, STRiP's Implementation, Computer Systems Laboratory, Stanford University, pp. 108-114 and 145-147 (Jul. 1992).
Greenstreet et al., "Self-Timed Iteration," Elsevier Science Publishers B.V. (North-Holland), pp. 309-322 (1988).
Hampel et al., "Threshold logic," IEEE Spectrum, pp. 32-39 (May 1971).
Heller et al., "Session I: Custom and Semi-Custom Design Techniques--WAM 1.3: Cascode Voltage Switch Logic: A Differential CMOS Logic Family," IEEE International Solid State Circuit Conference, 2 pgs. (1984).
Mead et al., "Introduction to VLSI Systems," Addison-Wesley Series in Computer Science, pp. 242-262 (1980).
Meng et al., "Automatic Synthesis of Asynchronous Circuits from High-Level Specifications," IEEE Transactions on Computer-Aided Design, vol. 8, No. 11, pp. 1185-1205 (Nov. 1989).
Muller, "Asynchronous Logics and Application to Information Processing," Switching Theory in Space Technology, pp. 289-297 (1963).
Nielsen et al., "A Low-power Asynchronous Data-path for a FIR filter bank," IEEE, pp. 197-207 (1996).
Renaudin et al., "The Design of Fast Asynchronous Adder Structures and their Implementation using D.C.V.S. Logic," International Symposium on Circuits and Systems, vol. 4, pp. 291-294 (undated).
Shibata et al., "A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations," IEEE Transactions on Electron Devices, vol. 39, No. 6, pp. 1444-1455 (Jun. 1992).
Singh, "A Design Methodology for Self-Timed Systems," Thesis, Massachusetts Institute of Technology, pp. 1-98 (Feb. 1981).
Sparso et al., "Design of delay insensitive circuits using multi-ring structures," EURO-DAC '92 European Design Automation Conference, IEEE, pp. 15-20 (1992).
Sparso et al., "Delay-insensitive multi-ring structures," Integration, the VLSI journal 15, pp. 313-340 (1993).
Sutherland, "Micropipelines," Communications of the ACM, vol. 32, No. 6, pp. 720-738 (Jun. 1989).
Unger, "Asynchronous Sequential Switching Circuits," Chapter 6, Department of Electrical Engineering, Columbia University, pp. 221-229 (1969).
Williams, "Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings," Technical Report No. CSL-TR-90-431, Computer Systems Laboratory, Stanford University, pp. 1-26 (Aug. 1990).
Williams, "Self-Timed Rings and their Application to Division/Chapters 1-7," Technical Report No. CSL-TR-91-482, Computer Systems Laboratory, Stanford University, pp. 1-144 (May 1991).
Wojcik et al., "On the Design of Three-Valued Asynchronous Modules," IEEE Transactions on Computers, vol. C-29, No. 10, pp. 889-898 (Oct. 1980).
Wuu et al., "Transaction Briefs--A Design of a Fast and Area Efficient Multi-Input Muller C-element," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, No. 2, pp. 215-219 (Jun. 1993).
Fant Karl M.
Parker David A.
Le Thien
Theseus Logic Inc.
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