Dynamic three-state bussing capability in a configurable logic a

Details Dynamic three-state bussing capability in a configurable logic a Dynamic three-state bussing capability in a configurable logic a

1993-02-05

1994-05-31

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, H03K 19177

Patent

active

053172094

ABSTRACT:
The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of rows of logic cells and a plurality of columns of logic cells. The array further includes at least one horizontally aligned local bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned local bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array also includes means for configuring the array such that any logic cell A in the array can write to a local bus which can be linked through the array's bussing network so that logic cell A can be read by any other logic cell B; correspondingly, logic cell B can write to a local bus which is linked through the same components such that data written by logic cell B can be read by logic cell A. Whether a logic element is reading from or writing to a local bus in controlled by a logic function created in the array. The configuration capability is due to means for placing the bus drivers in a high impedance state, means for bidirectional bussing capability due to extra passgates in the array repeaters, and means for connecting horizontal busses to vertical busses through the use of a core cell to bus interface.

REFERENCES:
patent: 4700187 (1987-10-01), Furtek
patent: 4870302 (1989-09-01), Freeman
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 4918440 (1990-04-01), Furtek
patent: 4935734 (1990-06-01), Austin
patent: 5019736 (1991-05-01), Furtek
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5155389 (1992-10-01), Furtek
patent: 5187393 (1993-02-01), El Gamal et al.
Sven Wahlstrom; Programmable Logic Arrays-Cheaper By The Millions; Electronics, Dec. 11, 1967, pp. 90-95.
R. C. Minnick; Survey of Microcellular Research; Stanford Research Institute; Scientific Report 1; Jul. 1966; SRI Project 5876.
Robert C. Minnick; A Survey of Microcellular Research; Journal of the Association for Computing Machinery, vol. 14, No. 2, Apr. 1967, pp. 203-241.
Richard G. Shoup; Programmable Cellular Logic Arrays; Computer Science Department Carnegie-Mellon Univ.; Mar. 1970.
Ivan Sutherland et al.; Large-Scale Integration Makes Logic Elements Fast and Cheap, . . . ; Microelectronics and Computer Science; Scientific American; Sep. 1977; vol. 237, No. 3; pp. 217-228.
Concurrent Logic, Inc. Data Sheet CFA6006 Field Programmable Gate Array; Advanced Info.; Mar. 15, 1991, Rev. 2.2.

Affiliated with

Also associated with

Rating

Dynamic three-state bussing capability in a configurable logic a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic three-state bussing capability in a configurable logic a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic three-state bussing capability in a configurable logic a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1629780