Dynamic system clocking and address decode circuits, methods and

Details Dynamic system clocking and address decode circuits, methods and Dynamic system clocking and address decode circuits, methods and

1997-05-16

1999-02-02

Donaghue, Larry D.

39575001, 39575005, 39575006, 39580032, 39580036, G06F 132

Patent

active

058677178

ABSTRACT:
A single-chip integrated circuit device (110) includes an on-chip bus (904) and a plurality of integrated circuit functional blocks (934, 932) having respective clock inputs connected to the on-chip bus (904). An address decoder (in 1210) is provided responsive to particular addresses to supply an output of a differing character (IDE/NON-IDE) depending on whether or not the particular addresses are received. A clock generating circuit (1201) having a control input (IDE/NON-IDE) fed by the output of the address decoder (in 1210) and a clock output (SYSCLK) connected to the on-chip bus (904) supplies a clock signal that depends in rate on whether or not the particular addresses are received. Other circuits, systems, and methods are disclosed.

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