Electrical pulse counters – pulse dividers – or shift registers: c – Particular transfer means – Including logic circuit
Patent
1982-05-21
1984-08-07
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Particular transfer means
Including logic circuit
377104, 377123, H03K 2106, H03K 2134, H03K 2322
Patent
active
044647735
ABSTRACT:
A first variant using conventional ratio-type two-phase design with nonoverlapping clock signals consists of a first inverter (I1), a complex gate (KG), a first transfer transistor (T1), a second inverter (I2), and a third inverter (I3) connected in series with respect to the signal flow. The complex gate (KG) consists of two NORed AND elements (U1, U2). The output of the second inverter (I2) is the count-up output (VA), and that of the third inverter (I3) is the count-down output (RA). The count-up output (VA) is coupled through a second transfer transistor (T3), controlled by the second clock signal (F2), to the first input of the first AND element (U1), whose second input is connected to the output of the first inverter (I1). The count-down output (RA) is coupled through a third transfer transistor (T2), controlled by the second clock signal (F2), to the first input of the second AND element (U2), whose second input is connected to the output of the NOR gate (NG) through a fourth transfer transistor (T 5), which is also controlled by the second clock signal (F2). One of the two inputs of the NOR gate is connected to the carry input (UE) in each stage. The carry input (UE) is connected to the carry output (UA) of the stage through a carry transfer transistor (UT). The carry input (UE) of the least significant stage is grounded. The second input of the NOR gate (NG) is connected to a stop line (S). The carry output (UA) is connected to a constant voltage (U) through a transfer transistor (T4) controlled by the countdown output (RA).
In a second variant, the complex gate (KG) is omitted, so that the output of the first inverter (I1') is connected directly to the input of the second inverter (I2') through the first transfer transistor (T1'). The output of the NOR gate (NG') controls the gate of the second transfer transistor (T2'). Its first input is fed with the first clock signal (F1'), and its second input is connected to the carry input (UE). Those ends of the current paths of the second and third transfer transistors (T2', T3') not connected to the outputs are coupled to the input of the inverter (I1').
REFERENCES:
patent: 3284645 (1966-11-01), Eichelberger et al.
patent: 3437832 (1969-04-01), Kopetski
patent: 4150305 (1979-04-01), Streit et al.
Backes Reiner
Neal Mathew
Schmidtpott Friedrich
Heyman John S.
IT&T Industries, Inc.
Lenkszus Donald J.
Raden James B.
LandOfFree
Dynamic synchronous binary counter with stages of identical desi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic synchronous binary counter with stages of identical desi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic synchronous binary counter with stages of identical desi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-606503