Amplifiers – Miscellaneous – Amplifier protection means
Reexamination Certificate
2000-07-24
2002-02-26
Pascal, Robert (Department: 2817)
Amplifiers
Miscellaneous
Amplifier protection means
C330S251000, C327S149000, C333S018000
Reexamination Certificate
active
06351184
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the power efficiency of switching amplifiers. More specifically, techniques are provided herein for improving the power efficiency of a switching amplifier by dynamically controlling its switching frequency.
In the switching amplifier
100
shown in
FIG. 1
, the input signal is modulated into one-bit digital data which is then used to control power stage MOSFETs M
1
and M
2
for power amplification. The amplified input signal is then recovered by a low pass filter comprising inductor L and capacitor C
AP
. Break-before-make circuitry
102
ensures that M
1
and M
2
are never turned on simultaneously and, as a result, there is no DC power consumption in the power stage. Thus, the power loss in amplifier
100
is largely attributable to switching loss due to the charging and discharging of the parasitic capacitance at the power stage, i.e., C
p
. This switching loss can be expressed as:
P
L
=C
p
×V
cc
2
×f
s
where C
p
is the total parasitic capacitance, V
cc
is the power supply voltage, and f
s
is the switching frequency.
To reduce the switching losses and thus increase the efficiency of amplifier
100
, any of these three quantities may be reduced, at least theoretically. However, in practice, because the power supply voltage determines the output power, it cannot be changed for a particular output power requirement. In addition, because C
p
is a parasitic value it is virtually uncontrollable. Therefore, as a practical matter, the most feasible way to reduce switching loss in a switching amplifier is by reducing its switching frequency.
FIG. 2
is a graph which illustrates the relationship between switching frequency and power efficiency for a switching amplifier. As shown in the figure, by reducing the switching frequency f
s
from sf
2
to sf
1
, a gain in power efficiency from PE
2
to PE
1
is realized.
However, as shown in
FIG. 3
, when the switching frequency of a switching amplifier is below f
t
, decreases in switching frequency are accompanied by corresponding decreases in the amplifier's output dynamic range. Thus, to avoid a loss of dynamic range, the amplifier's switching frequency should be kept at or above f
t
.
It is therefore desirable to provide techniques by which the switching frequency of a switching amplifier may be controlled such that power efficiency is improved without unacceptable losses in dynamic range.
SUMMARY OF THE INVENTION
According to the present invention, techniques are provided by which the switching frequency of a switching amplifier is controlled to get a desired power efficiency. A dynamic delay line is inserted in the feedback loop of the switching amplifier and is controlled to maintain the loop delay of the amplifier equal to a reference delay. The delay line is controlled by delay detection circuitry which monitors the loop delay, compares it to the reference delay, and controls the delay line in 10 ns increments to bring the actual loop delay in line with the reference delay.
Thus, the present invention provides a method for controlling a switching frequency associated with a switching amplifier in which an actual loop delay associated with the switching amplifier is dynamically controlled to correspond to a reference loop delay.
According to another embodiment, a method for controlling a switching frequency associated with a switching amplifier is provided. An actual loop delay associated with the switching amplifier is monitored. The actual loop delay is compared with a reference loop delay. A delay line in the switching amplifier is dynamically controlled such that the actual loop delay corresponds to the reference loop delay.
According to yet another embodiment, a switching amplifier is provided which includes an input stage having a first node associated therewith and a power stage having a second node associated therewith. An actual loop delay is defined with reference to the first and second nodes. Delay detection circuitry compares the actual loop delay to a reference loop delay. A dynamic delay line controlled by the delay detection circuitry controls the actual loop delay to correspond to the reference loop delay.
According to a still further embodiment, a switching amplifier is provided. An input stage generates a switching signal and has a first node associated therewith. Break-before-make circuitry generates two drive signals from the switching signal. A power stage includes two switches which are alternately driven by the two drive signals and which has a second node associated therewith. An actual loop delay is defined with reference to the first and second nodes. A continuous-time feedback path is provided from the power stage to the input stage. Delay detection circuitry compares the actual loop delay to a reference loop delay. A dynamic delay line controlled by the delay detection circuitry controls the actual loop delay to correspond to the reference loop delay.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
REFERENCES:
patent: 3931581 (1976-01-01), Kush, Jr. et al.
patent: 4326170 (1982-04-01), Levy
patent: 4604591 (1986-08-01), Vasile
patent: 4673887 (1987-06-01), Atherton
patent: 5896066 (1999-04-01), Katayama et al.
patent: 5963086 (1999-10-01), Hall
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6194932 (2001-02-01), Takemae et al.
Delano Cary L.
Miao Guoqing
Beyer Weaver & Thomas LLP.
Choe Henry
Pascal Robert
Tripath Technology Inc.
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