Dynamic switching arrangement for error masking in a system for

Details Dynamic switching arrangement for error masking in a system for Dynamic switching arrangement for error masking in a system for

1991-04-29

1993-08-17

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

375 40, 375100, H04B 100

Patent

active

052373185

ABSTRACT:
Input frames TAR, TARB of each of two diversity digital channels, shifted randomly in time, are applied to respective variable delay memories, which in turn provide in-phase frames on the selection terminals of an output switch. An error masking circuit, including an error detector having various levels of error gravity, and a priority encoder for comparing errors between the two channels and an R-S flip-flop, is connected between each input terminal and a switch control terminal. The better quality frame of the two digital channels is selected and provided as the output signal of the dynamic switching circuitry.

REFERENCES:
patent: 4380814 (1983-04-01), Shinmyo
patent: 4799237 (1989-01-01), Itoh
patent: 4827490 (1989-05-01), Guerin
patent: 4926498 (1990-05-01), Suzuki et al.
patent: 5065411 (1991-11-01), Muto

Affiliated with

Also associated with

Rating

Dynamic switching arrangement for error masking in a system for does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic switching arrangement for error masking in a system for , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic switching arrangement for error masking in a system for will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2247252