Dynamic slew-rate booster for CMOS-opamps

Details Dynamic slew-rate booster for CMOS-opamps Dynamic slew-rate booster for CMOS-opamps

2002-03-26

2003-03-04

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S067000, C327S335000, C327S563000

Reexamination Certificate

active

06529048

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to opamps with a dynamic slew-rate booster.
BACKGROUND OF THE INVENTION
The analog core of pipeline high-speed, high-resolution analog-to-digital converters (ADCs) requires the adoption of opamps both very fast and with high gain. While the prior art opamp designs often seem to be optimized if inspected via AC simulations, these opamps reveal an insufficient load charging performance at a subsequent transient analysis, and do not settle properly in the few nanoseconds available. This shortcoming has been verified both on rising and falling transitions of the differential output of opamps using active loads.
The prior art approach to opamp speed-up encompasses increasing the current in the stage (leads to swing and power consumption issues), enlarging the transistors' size (area occupation, and parasitics worsening), or shrinking the external capacitors (conflicts with kT/C noise floor limits). Moreover, bulky output buffer stages harm the stability of the opamp loop.
SUMMARY OF THE INVENTION
An opamp with a slew rate booster includes a first high side transistor coupled to a first differential output node; a second high side transistor coupled to a second differential output node; a first booster circuit coupled to the control node of the first high side transistor; a second booster circuit coupled to the control node of the second high side transistor. The opamp exploits the gate control available on the high side transistors
23
and
26
. During the charge-discharge differential transient of the load capacitances
58
and
60
, the circuit increases the current given by the high side transistor
23
or
26
that is pulling up its output OUT− or OUT+, and reduces by the same amount the current provided at the other output OUT+ or OUT− that is being pulled down by a low side driver
43
or
40
. The gate control is accomplished through a simple, symmetrical capacitor-resistor network that implements a basic differentiator.


REFERENCES:
patent: 3643108 (1972-02-01), Pilkington
patent: 3882326 (1975-05-01), Kruggel
patent: 5293514 (1994-03-01), Nakagawara
patent: 5298801 (1994-03-01), Vorenkamp et al.
patent: 5345346 (1994-09-01), Brannon et al.
patent: 5418498 (1995-05-01), DeVito et al.
patent: 5917377 (1999-06-01), Asazawa
K. Nagaraj, “CMOS Amplifiers Incorporating a Novel Slew Rate Enhancement Technique” IEEE, pp. 11.6.1-11.6.5, 1990.
F. Yang, P. Loumeau, P. Senn, “Novel Output Stage for DC Gain Enhancement of Opamp and OTA”, Electronic Letters, vol. 29, No. 11, pp. 958-959, May 27, 1993.

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