Dynamic single bit per cell to multiple bit per cell memory

Details Dynamic single bit per cell to multiple bit per cell memory Dynamic single bit per cell to multiple bit per cell memory

1996-09-10

2000-08-01

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

365168, G11C 1604

Patent

active

060976373

ABSTRACT:
A memory system having memory cells for storing one of a plurality of threshold levels to store more than a single bit per cell is disclosed. The memory system contains a switch control to permit selection of an operating mode including a multi-level cell mode and a standard cell mode. The memory system further includes a reading circuit to read a single bit per cell when operating in the standard cell mode, and to read multiple bits of data per memory cell when operating in the multi-level cell mode. A program circuit programs a single bit of data per memory cell for addressed memory cells when operating in the standard cell mode, and programs multiple bits of data per memory cell for addressed memory cells when operating in the multi-level cell mode.

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