Dynamic signal loop resolution in a compiled cycle based circuit

Details Dynamic signal loop resolution in a compiled cycle based circuit Dynamic signal loop resolution in a compiled cycle based circuit

1996-12-06

1999-09-28

Beausoliel, Jr., Robert W.

39518309, 39518321, 395578, G06F 1127

Patent

active

059601710

ABSTRACT:
A compiled cycle based circuit simulator efficiently implements dynamic loop resolution at execution time. A static loop arises when a plurality of signals appear to be interdependent. In a properly designed circuit, apparent looping of signals is usually protected by other mutually exclusive signals. A dynamic loop exists when the signals are actually interdependent. A cyclic clock is divided into a fixed plurality of time slots. During each time slot that a plurality of interrelated signals can change, code for the interdependent signals used by other logic or memory elements are demand generated as function calls. Within each such called function, computation of dependent interdependent signals is by function call protected by control signals. Nondynamic static looping of signals is thus efficiently ignored. Dynamic looping is detected and reported through monitoring of function call depth.

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Weber et al. Periodic Signal Suppression in a Concurrent Fault Simulator (IEEE, 5 pages) 1991.

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