Dynamic shift register circuit

Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Particular transfer means

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377 81, 307482, G11C 1928, H03K 2322

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active

044465670

ABSTRACT:
A dynamic shift register circuit comprises an input terminal and an output terminal. It further comprises a first transfer gate circuit connected to the input terminal for receiving an input signal and transferring the input signal under the control of a first clock signal; an inverter circuit for inverting a level of an output signal of the first transfer gate circuit; a second transfer gate circuit connected to the inverter circuit for receiving an output signal of the inverter circuit and transferring the same under the control of a second clock signal which has a level opposite to that of the first clock signal; a signal follower circuit for producing an output signal having a level which follows a level of the output signal of the first transfer gate circuit; and a logic circuit connected to first and second power source voltages. The logic circuit is made operative by an output signal of the signal follower circuit and produces an inverter function at the output terminal, in response to an output signal of the second transfer gate circuit. The logic circuit comprises a capacitor element one terminal of which is connected to the output terminal of the signal follower circuit and the other terminal of which is connected to said output terminal of the dynamic shift register.

REFERENCES:
patent: 3588526 (1971-06-01), Cricchi
patent: 3683203 (1972-08-01), Smith
patent: 3829711 (1974-08-01), Crowle
patent: 3898479 (1975-08-01), Proebsting
patent: 3916169 (1975-10-01), Cochran et al.
patent: 4354123 (1982-10-01), Eaton, Jr.
Pages 129-132 of Chapter 5, "Shift Registers for Data Delay, Logic, and Memory" of the Book MOS/LSI Design and Application by William N. Car et al.

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