Dynamic semiconductor memory with block decoding

Details Dynamic semiconductor memory with block decoding Dynamic semiconductor memory with block decoding

1989-03-14

1991-07-02

Moffitt, James W.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523005, G11C 700

Patent

active

050291416

ABSTRACT:
The dynamic semiconductor memory device comprises a plurality of write block selecting lines and a plurality of read block selecting lines for selecting any one of the memory cell groups, a plurality of write row selecting lines for selecting any memory cells for a word in one of the memory cell groups selected by the write block selecting lines, a purality of first logic gates connected at one input terminals thereof to the write block selecting lines and at the other input terminals thereof to the write row selecting lines, a plurality of divisional write word lines each connecting an output terminal of one of the first logic gates in parallel to the corresponding memory cells for a word, a plurality of read row selecting lines for selecting any memory cells for a word in one of the memory cell groups selected by the read block selecting lines, a plurality of second logic gates connected at one input terminals thereof to the read block selecting lines and at the other input terminals thereof to the read row selecting lines, and a plurality of divisional read word lines each connecting an output terminal of one of the second logic gates in parallel to the corresponding memory cells for a word.

REFERENCES:
patent: 4554646 (1985-11-01), Yoshimoto et al.
patent: 4935896 (1990-06-01), Matsumura et al.
"Introduction to NMOS and CMOS VLSI System Design", pp. 268-273.

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