Dynamic semiconductor memory device having fast operation mode a

Details Dynamic semiconductor memory device having fast operation mode a Dynamic semiconductor memory device having fast operation mode a

1996-05-21

1997-09-16

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

3652335, G11C 800

Patent

active

056687745

ABSTRACT:
A semiconductor memory device includes a delay stage for delaying a row address strobe signal ZRAS by a predetermined time, a first signal generating circuit for generating a signal instructing activation/precharge of an array in accordance with the row address strobe signal ZRAS, and a second signal generating circuit for generating a signal setting the output stage to an output high impedance state in accordance with a delayed row address strobe signal ZRAS from the delay stage and a column address strobe signal ZCAS. Even if both the column address strobe signal and row address strobe signal may be simultaneously set to the high and low levels, respectively, the column address strobe signal and the delayed row address strobe signal are not simultaneously set to the high level, so that the output stage is prevented from attaining the high impedance state, and data output is allowed. Therefore, the semiconductor memory device can operate fast with a low current consumption.

REFERENCES:
patent: 5319607 (1994-06-01), Fuji et al.
"A 100ns 64K Dynamic RAM using Redundancy Techniques," Eaton et al., 1981 IEEE International Solid-State Circuits Conference, pp. 84-85.
"Pentium specific Burst EDO appears in 1996," Kurata, Nikkei Byte/Apr. 1995, pp. 141-143.
"A 256 DRAM with Descrambled Redundancy Test Capability," Kantz et al., 1984 IEEE International Solid-State Circuits Conference, pp. 272-273.

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