Dynamic semiconductor memory device having excellent charge rete

Details Dynamic semiconductor memory device having excellent charge rete Dynamic semiconductor memory device having excellent charge rete

1998-10-29

2000-08-01

Zarabian, A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, B11C 800

Patent

active

060976659

ABSTRACT:
Level converter converts a word line group specifying signal, which is sent from a row decoder and has amplitude of a power supply potential Vcc and a ground potential GND, into mutually complementary logic signals WD and ZWD of a high voltage Vpp and a negative potential Vbb. An RX decoder decodes an address signal to output a signal of an amplitude of (Vpp-Vbb) specifying a word line in a word line group. A word driver provided corresponding to each word line transmits a word line specifying signal or a negative potential to the corresponding word line in accordance with signals WD and ZWD sent from a level converting circuit. The nonselected word line receives negative potential Vbb from a word driver. The selected word line receives high voltage Vpp from the word driver. It is possible to suppress a channel leak current at a memory transistor in the nonselected memory cell, which may be caused by the potential change of the word line and/or bit line, and a charge holding characteristic of the memory cell can be improved.

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Y. Nakagome et al., "Sub-1-V Swing Bus Architecture for Future Low-Power ULSIs", 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 82-83.

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