Dynamic semiconductor memory device having excellent charge...

Details Dynamic semiconductor memory device having excellent charge... Dynamic semiconductor memory device having excellent charge...

1999-12-21

2002-04-23

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110

Reexamination Certificate

active

06377508

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a dynamic semiconductor memory device storing information in the form of electric charges. More particularly, the invention relates to a structure in a dynamic semiconductor memory device for improving charge retention characteristics of memory cells. More specifically, the invention relates to a structure of circuitry for selecting word lines.
2. Description of the Background Art
FIG. 63
schematically shows a whole structure of a dynamic semiconductor memory device (will be referred to as “DRAM”) in the prior art. In
FIG. 63
, the DRAM includes a memory cell array
900
having memory cells MC arranged in a matrix of rows and columns. In memory cell array
900
, a word line WL is provided corresponding to each row of memory cells MC, and a column line (bit line pair BL and /BL) is provided corresponding to each column of memory cells MC.
FIG. 63
representatively shows one word line WL and one bit line pair BL and /BL. Memory cell MC is provided corresponding to a crossing of bit line pair BL and /BL and word line WL. In
FIG. 63
, memory cell MC is provided corresponding to the crossing of bit line BL and word line WL, as an example. Memory cell MC includes a capacitor MQ storing information in the form of electric charges, and a memory transistor MT which is responsive to a signal potential on word line WL to be turned on to connect memory capacitor MQ to bit line BL (or /BL).
The DRAM further includes an address buffer
902
which produces an internal address signal from an externally applied address signal, a row decode circuit
904
which decodes the internal row address signal sent from address buffer
902
to produce a decode signal specifying a corresponding word line in memory cell array
900
, and a word line drive circuit
906
which transmits a signal voltage indicative of the selected state onto the corresponding word line in accordance with the row decode signal from row decode circuit
904
. Word line drive circuit
906
, of which specific structure will be described later, transmits a high voltage Vpp higher than an operation power supply potential Vcc onto the selected word line (i.e., word line corresponding to the row specified by the address signal).
The DRAM further includes a sense amplifier group or band
908
including a plurality of sense amplifiers which are provided corresponding to respective bit line pairs BL and /BL, and differentially amplify signal potentials on the corresponding bit line pairs, a column decoder
910
which decodes the internal column address signal from address buffer
902
to produce a column select signal specifying a corresponding column (bit line pair) in memory cell array
900
, an I/O gate circuit
912
which operates in accordance with the column select signal from column decoder
910
to connect the corresponding column (bit line pair) in the memory cell array to an internal data line (internal I/O line)
913
, and an I/O circuit
914
for inputting and outputting external data DQ.
I/O gate circuit
912
includes column select gates provided corresponding to the respective bit line pairs. Upon writing of data, I/O circuit
914
produces internal write data from externally applied data DQ, and transmits the same to internal data line
913
. Upon reading of data, I/O circuit
914
produces external read data DQ from internal read data on internal data line
913
. In
FIG. 63
, I/O circuit
914
is shown to perform input and output of data through the same pin terminal. However, I/O circuit
914
may be adapted to perform input and output of data through different pin terminals.
For determining a timing of internal operation of the DRAM, there is provided a control signal generating circuit
916
. Control signal generating circuit
916
receives a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and an output enable signal /OE, and generates various internal control signals. In
FIG. 63
, control signal generating circuit
916
is shown to apply internal control signals to address buffer
902
and row decoder
904
.
When the row address strobe signal /RAS is activated, it attains the L-level and designates start of the memory cycle (start of access to the DRAM), and enables latching and decoding of the address signal, respectively, by address buffer
902
and row decode circuit
904
. Address buffer
902
latches the address signal and produces the internal row address signal to apply the same to row decode circuit
904
when row address strobe signal /RAS attains the L-level. Row address strobe signal /RAS controls the operation of circuitry related to selection of a row in memory cell array
900
.
Column address strobe signal /CAS determines the timing of operations related to column selection. When signal /CAS attains the L-level, address buffer
902
latches the externally applied address signal and produces the internal column address signal to apply the same to column decoder
910
. Column decoder
910
decodes the applied address signal in accordance with the L-level of signal /CAS.
When activated, write enable signal /WE attains the L-level and indicates that the data write operation is designated. When activated, output enable signal /OE attains the L-level and designates that data of a selected memory cell is to be read out. Now, selecting operation of a memory cell of one bit will be briefly described below.
In response to the fall of signal /RAS, address buffer
902
takes in the externally applied address signal to produce the internal row address signal under the control by control signal generating circuit
916
. Row decoder
904
decodes the internal row address signal thus produced under the control by control signal generating circuit
916
, and produces a word line designating signal designating a word line WL. Word line drive circuit
906
raises the potential of the addressed word line WL in accordance with the word line designating signal from row decode circuit
904
. As will be detailed later, word line drive circuit
906
raises the potential of the selected word line to high voltage Vpp higher than operation power supply voltage Vcc. The reason of boosting the potential of a selected word line will also be detailed later.
Memory transistor MT contained in memory cell MC connected to the selected word line is turned on to connect memory cell capacitor MQ to bit line BL (or /BL). The potential of bit line BL (/BL), which is kept in an electrically floating state at the intermediate potential Vcc/2 changes in accordance with information (accumulated electric charges) stored in memory capacitor MQ.
The sense amplifier contained in sense amplifier band
908
is activated under the control by control signal generating circuit
916
, to amplify and latch the potential difference of each bit line pair BL and /BL.
When signal /CAS attains the L-level, address buffer
902
latches the externally applied address signal and produces the internal column address signal to apply the same to column decoder
910
. Column decoder
910
is activated under the control by control signal generating circuit
916
to decode the internal column address signal from address buffer
902
and generate the column select signal specifying a corresponding column (bit line pair) in memory cell array
900
.
I/O gate circuit
912
selects the corresponding column (bit line pair) in accordance with the column select signal from column decoder
910
, and connects the selected column (bit line pair) to internal data line
913
.
Writing and reading of data are performed depending on signals /WE and /OE. In the data writing operation, signal /WE attains the L-level, and I/O circuit
914
produces internal write data from externally applied write data D and transmits the internal write data onto the selected column via internal data line
913
and I/O gate circuit
912
. In the data reading operation, signal /OE attains the L-level, and I/O circuit
91

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