Static information storage and retrieval – Format or disposition of elements
Patent
1994-07-08
1997-07-01
Gossage, Glenn
Static information storage and retrieval
Format or disposition of elements
365 63, 365 72, 365205, 365208, G11C 502, G11C 11407, G11C 11413
Patent
active
056445253
ABSTRACT:
A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.
REFERENCES:
patent: 3942164 (1976-03-01), Dunn
patent: 4351034 (1982-09-01), Eaton, Jr. et al.
patent: 4367540 (1983-01-01), Shimohigashi
patent: 4402063 (1983-08-01), Wittwer
patent: 4584672 (1986-04-01), Schutz et al.
patent: 4586171 (1986-04-01), Fujishima
patent: 4730280 (1988-03-01), Aoyama
patent: 4800525 (1989-01-01), Shah et al.
patent: 4825417 (1989-04-01), Seo
patent: 4825418 (1989-04-01), Itoh et al.
patent: 4829483 (1989-05-01), Ogihara
patent: 4903394 (1990-02-01), Inoue
patent: 4922459 (1990-05-01), Hidaka
patent: 4958325 (1990-09-01), Nakagome et al.
IEEE Journal of Solid-State Ciruits, vol. SC-20, No. 5, Oct. 1985, pp.909-912, "A Reliable 1-Mbit DRAM With a Multi-Bit-Test Mode", Kumanoya et al.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, "A 4-Mbit DRAM With Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor (FASIC) Cell" pp. 643-650, Mashiko et al.
Oowaki Yukihito
Takashima Daisaburo
Tsuchida Kenji
Gossage Glenn
Kabushiki Kaisha Toshiba
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