Static information storage and retrieval – Powering
Reexamination Certificate
1999-06-30
2001-01-16
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Powering
C365S227000
Reexamination Certificate
active
06175531
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a dynamic semiconductor memory device of a random access type (DRAM/SDRAM) having an initialization circuit which controls a switch-on operation of the semiconductor memory device and of its circuit components and supplies a supply voltage stable signal (POWERON) once the supply voltage has been stabilized after the switch-on of the semiconductor memory device. The invention also relates to a method for initializing such a dynamic semiconductor memory device, and also to the use of an enable circuit, which supplies an enable signal, for controlling the switch-on operation of a dynamic semiconductor memory device.
In the case of SDRAM semiconductor memories according to the JEDEC standard, it is necessary to ensure during the switch-on operation (“POWERUP”) that the internal control circuits provided for the proper operation of the semiconductor memory device are reliably held in a defined desired state, in order to prevent undesirable activation of output transistors that would cause, on the data lines, a short circuit (so-called “bus contention” or “data contention”) or uncontrolled activation of internal current loads. The solution to the problem turns out to be difficult on account of a fundamental unpredictability of the time characteristic of the supply voltage and of the voltage level or levels at the external control inputs during the switch-on operation of the semiconductor memory. According to the specifications of the manufacturer, an SDRAM component should ignore all commands that are present chronologically before a defined initialization sequence. The sequence consists of predetermined commands that must be applied in a defined chronological order. However, a series of functions and commands which are allowed during proper operation of the component are desired or allowed chronologically only after the initialization sequence. According to the JEDEC standard for SDRAM semiconductor memories, a recommended initialization sequence (so-called “POWERON-SEQUENCE”) is provided as follows:
a) the application of a supply voltage and a start pulse in order to bring about an NOP condition at inputs of the component;
b) the maintenance of a stable supply voltage of a stable clock signal, and of stable NOP input conditions for a minimum time period of 200 &mgr;s;
c) the preparation command for word line activation (PRECHARGE) for all the memory banks of the device;
d) the activation of two or more refresh commands (AUTOREFRESH); and
4) the activation of the loading configuration register command (MODE-REGISTER-SET) for initializing the mode register.
After the identification of such a defined initialization sequence, the memory module is normally in a so-called IDLE state, that is to say it is precharged and prepared for proper operation. In the case of the SDRAM semiconductor memory modules that have been disclosed to date, all the control circuits of the component have been unlatched only with the POWERON signal. The signal POWERON is active if the internal supply voltages have reached the necessary values that are necessary for the proper operation of the component. The module is then in a position to recognize and execute instructions.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a dynamic semiconductor memory device and a method for initializing a dynamic semiconductor memory device which overcomes the above-mentioned disadvantages of the prior art methods and devices of this general type, which is as simple as possible in structural terms in the control of the switch-on operation in dynamic semiconductor memory devices of the random access type (DRAM or SDRAM), and which effectively prevents the risk of a short circuit of the data lines and/or of uncontrolled activation of internal current loads.
With the foregoing and other objects in view there is provided, in accordance with the invention, a dynamic semiconductor memory device of a random access type, including an initialization circuit controlling a switch-on operation and supplying a supply voltage stable signal once a supply voltage has been stabilized after a start of the switch-on operation. The initialization circuit has a control circuit for controlling operations and an advance detector circuit detecting a predetermined level state of an externally applied clock control signal chronologically before a generation of the supply voltage stable signal and in response to the externally applied clock control signal the advance detector circuit supplying an enable signal for unlatching said control circuit.
The object is achieved by a dynamic semiconductor memory device which supplies a further or second enable signal (CHIPREADY) for controlling the switch-on operation of such a semiconductor memory device.
The invention provides for the initialization circuit to have an advance detector circuit, which detects a predetermined level state of an externally applied clock control signal (CKE) chronologically before the supply voltage stable signal (POWERON) and, as a reaction to a first level change (L-H transition), supplies a first enable signal for unlatching the control circuit provided for the proper operation of the semiconductor memory device. In particular, by the initialization circuit according to the invention, the first level change of the clock control signal (CKE) to the logic HIGH state, that is to say the active state, is detected and the first enable signal is output as a reaction. The clock control signal (CKE) is normally at the logic level state LOW, that is to say the inactive state, from the outset. The invention results in the earliest possible detection of the level change of the clock control signal (CKE) to logic HIGH. The level change, together with the activation of the supply voltage stable signal POWERON from inactive to active (active state=logic “HIGH”) and the proper initialization sequence, effecting the triggering of the second enable signal CHIPREADY. As a result, the advance detector circuit is in a position, even before the provision of the POWERON signal by other circuit sections of the semiconductor chip, to identify the predetermined level, in particular the LOW level, of the clock control signal (CKE).
According to a particularly preferred embodiment of the invention, the clock control signal is to be understood to be the signal CKE (“input-clock-enable”) in the case of synchronous DRAM memory components, which signal, as is known, serves to activate the CLK signal (“input-clock”=master-clock-signal) if CKE=HIGH, and to deactivate it if CKE LOW. As is known, the POWERDOWN mode, the SELF-REFRESH mode or the SUSPEND mode is initialized by deactivation of the clock signal, that is to say CKE=LOW.
The signal POWERON indicates the provision of all the on-chip supply voltages in a manner known per se.
Following the principle of the invention, in addition to the regular receiver circuit that is provided in any case in the initialization circuit and is normally operated with a reference voltage, an additional receiver circuit or advance detector circuit is provided. The additional receiver circuit is operated independently of a reference voltage and remains permanently switched on at least during the POWERUP phase of the memory component. The additional receiver circuit is thus in a position to detect the first transition to the logic HIGH state, that is to say active state (in general: a predetermined level state), of the clock control signal CKE early on during the switch-on operation of the semiconductor memory device (POWERUP phase), to be precise even before the supply voltage stable signal POWERON changes from inactive to active. With the inactive state of the clock control signal CKE, the first enable signal supplied by the additional advance detector circuit latches the second enable signal CHIPREADY. Since the command signals (inter alia CS, RAS, CAS, WE) externally applied to the semiconductor memory device are undefined during the switch
Buck Martin
Fischer Helmut
Hemmert Heinrich
Johnson Bret
Kuhne Sebastian
Greenberg Laurence A.
Le Vu A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
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