Dynamic semiconductor memory device

Details Dynamic semiconductor memory device Dynamic semiconductor memory device

1994-12-13

1996-09-10

Popek, Joseph A.

Static information storage and retrieval

Format or disposition of elements

365 63, 365206, G11C 700

Patent

active

055552030

ABSTRACT:
A NAND type DRAM includes a plurality of NAND cells disposed on intersections between a plurality of word lines and a plurality of bit lines, a plurality of sense amplifiers each for sensing and amplifying the potential difference between two bit lines of each bit line pair among the plurality of bit lines, first switching sections for sequentially selecting those bit lines of the plurality of bit lines which are connected to the sense amplifier in a paired form, and second switching sections for sequentially changing the combination of a bit line pair constructed by bit lines selected by the first switching sections, and two bit lines disposed adjacent to and on both sides of a bit line to which the NAND cell is electrically connected are connected to the sense amplifier in a paired form by the first and second switching sections.

REFERENCES:
patent: 4807194 (1989-02-01), Yamada et al.
patent: 4872142 (1989-10-01), Hannai
patent: 5014241 (1991-05-01), Asakura et al.
patent: 5369612 (1994-11-01), Furuyama
patent: 5418750 (1995-05-01), Shiratake et al.
Takehiro Hasegawa, et al., "An Experimental DRAM with a HAND-Structured Cell", ISSCC 93 Digest of Technical Papers, Feb. 24, 1993 pp. 46-47.

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