Dynamic selection control in a memory

Details Dynamic selection control in a memory Dynamic selection control in a memory

1997-01-27

1998-01-13

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

3652335, 36518911, 365203, 365204, G11C 1606

Patent

active

057086044

ABSTRACT:
A driving circuit for a final decoding stage of an EPROM, EEPROM or FLASH EPROM for battery powered apparatuses functioning at relatively low supply voltage avoids energy absorption from a commonly boosted voltage node by switching the capacitance of the control node of the p-channel pull-up device of the CMOS inverter that drives the memory line and which constitutes the load of the driving circuit. The node is effectively charged by drawing current from the supply node and is discharged rapidly by switching in parallel thereto a previously discharged capacitance. This charge-sharing switcheable capacitance may advantageously be the capacitance of a similar p-channel pull-up control node of a deselected wordline of the array.

REFERENCES:
patent: 5631865 (1997-05-01), Iwase et al.
Motomu Ukita et al., IEEE International Solid State Circuits Conference, vol. 36, Feb. 1993, p. 252-253, XP000388097, "A Single Bitline Cross-Point Cell Activation (SCPA) Architecture for Ultra Low Power SRAMs".

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