Dynamic scan circuit and method for using the same

Details Dynamic scan circuit and method for using the same Dynamic scan circuit and method for using the same

1996-07-30

1997-04-08

Canney, Vincent P.

Excavating

39518306, G06F 1100

Patent

active

056195117

ABSTRACT:
The present disclosure describes a scan latch which utilizes dynamic interface nodes to facilitate full scan operation with a reduced number of transistors. A scan latch slave stage is coupled to a storage node of a storage device to capture data from that device. The scan latch slave device has an output driver with an input node coupled by a pass gate to the storage node. A scan clock line is coupled to the pass gate and to an enable input of the output driver. A slave scan clock signal received on the scan clock line enables the output driver and controls the pass gate. A master stage which may be utilized with the scan latch slave stage has a tri-state input device coupled to a serial input. The tri-state input device is controlled by a master scan clock and has an output coupled to the storage node.

REFERENCES:
patent: 4947357 (1990-08-01), Stewart et al.
patent: 5068603 (1991-11-01), Mahoney
Dobberpuhl, et al., "A 200-MHz 64-b Dual-Issue CMOS Microprocessor", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1555-1565.
Levitt, et al., "Testability, Debuggability, and Manufacturability Features of the UltraSPARC.TM.-I Microprocessor", International Test Conference, 1995, Paper 6.2, pp. 157-166.
Gerosa, et al., "A 2.2 W, 80 MHz Superscalar RISC Microprocessor", IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1440-1454 .

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