Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2001-09-10
2004-05-18
Liu, Shuwang (Department: 2634)
Pulse or digital communications
Equalizers
Automatic
C375S229000, C375S231000, C375S233000, C375S350000, C708S322000
Reexamination Certificate
active
06738419
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods and systems for regulating the power consumption of a communication system. More particularly, the invention relates to a method and a system for dynamically balancing power consumption against system performance requirements in a high-speed communication system operating at gigabit rates.
BACKGROUND OF THE INVENTION
Local Area Networks (LAN) provides network connectivity for personal computers, workstations and servers. Ethernet, in its original 10BASE-T form, remains the dominant network technology for LANs. However, among the high speed LAN technologies available today, Fast Ethernet, or 100BASE-T, has become the leading choice. Fast Ethernet technology provides a smooth, non-disruptive evolution from the 10 megabits per second (Mbps) performance of the 10BASE-T to the 100 Mbps performance of the 100BASE-T. The growing use of 100BASE-T connections to servers and desktops is creating a definite need for an even higher speed network technology at the backbone and server level.
The most appropriate solution to this need, now in development, is Gigabit Ethernet. Gigabit Ethernet will provide 1 gigabit per second (Gbps) bandwidth with the simplicity of Ethernet at lower cost than other technologies of comparable speed, and will offer a smooth upgrade path for current Ethernet installations.
In a Gigabit Ethernet communication system that conforms to the 1000BASE-T standard, gigabit transceivers are connected via Category 5 twisted pairs of copper cables. Cable responses vary drastically among different cables. Thus, the computations, and hence power comsumption, required to compensate for noise (such as echo, near-end crosstalk, far-end crosstalk) will vary widely depending on the particular cable that is used.
In integrated circuit technology, power consumption is generally recognized as being a function of the switching (clock) speed of transistor elements making up the circuitry, as well as the number of component elements operating within a given time period. The more transistor elements operating at one time, and the higher the operational speed of the component circuitry, the higher the relative degree of power consumption for that circuit. This is particularly relevant in the case of Gigabit Ethernet, since all computational circuits are clocked at 125 Mhz (corresponding to 250 Mbps per twisted pair of cable), and the processing requirements of such circuits require rather large blocks of computational circuitry, particularly in the filter elements. Power consumption figures in the range of from about 4.5 Watts to about 6.0 Watts are not unreasonable when the speed and complexity of modern gigabit communication circuitry is considered.
Pertinent to an analysis of power consumption is the realization that power is dissipated, in integrated circuits, as heat. As power consumption increases, not only must the system be provided with a more robust power supply, but also with enhanced heat dissipation schemes, such as heat sinks (dissipation fins coupled to the IC package), cooling fans, increased interior volume for enhanced air flow, and the like. All of these dissipation schemes involve considerable additional manufacturing costs and an extended design cycle due to the need to plan for thermal considerations.
Prior high speed communication circuits have not adequately addressed these thermal considerations, because of the primary necessity of accommodating high data rates with a suficient level of signal quality. Prior devices have, in effect, “hard wired” their processing capability, such that processing circuitry is always operative to maximize signal quality, whether that degree of processing is required or not. Where channel quality is high, full-filter-tap signal processing more often obeys the law of diminishing returns, with very small incremental noise margin gains recovered from the use of additional large blocks of active filter circuitry.
This trade-off between power consumption and signal quality has heretofore limited the options available to an integrated circuit communication system designer. If low power consumption is made a system requirement, the system typically exhibits poor noise margin or bit-error-rate performance. Conversely, if system performance is made the primary requirement, power consumption must fall where it may with the corresponding consequences to system cost and reliability.
Accordingly, there is a need for a high speed integrated circuit communication system design which is able to accomodate a wide variety of worst-case channel (cable) responses, while adaptively evaluating signal quality metrics in order that processing circuitry might be disabled, and power consumption might thereby be reduced, at any such time that the circuitry is not necessary to assure a given minimum level of signal quality.
Such a system should be able to adaptively determine and achieve the highest level of signal quality consistent with a given maximum power consumption specification. In addition, such a system should be able to adaptively determine and achieve the lowest level of power consumption consistent with a given minimum signal quality specification.
SUMMARY OF THE INVENTION
The present invention is a method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.
In particular, the first and second performance parameters are distinct and are chosen from the parametric group consisting of power consumption and a signal quality figure of merit. The signal quality figure of merit is evaluated while selected blocks of the multiplicity of processing blocks are disabled. The set of selected blocks which give the lowest power consumption, when disabled, while at the same time maintaining an acceptable signal quality figure of merit at a pre-defined threshold level is maintained in a disabled condition while the integrated circuit is subsequently operated.
In one aspect of the present invention, reduced power dissipation is chosen as the most desirable metric to evaluate, while a signal quality figure of merit is accorded secondary consideration. Alternatively, a signal quality figure of merit is chosen as the most desirable metric to evaluate, while power dissipation is accorded a secondary consideration. In a further aspect of the present invention, both signal quality and power dissipation are accorded equal consideration with selective blocks of the multiplicity of processing blocks being disabled and the resultant signal quality and power dissipation figures of merit being evaluated so as to define a co-existing local maxima of signal quality with a local minima of power dissipation.
In one particular embodiment, the present invention may be characterized as a method for dynamically regulating the power consumption of a communication system which includes at least a first module. The first module can be any circuit block, not necessarily a signal processing block. Power regulation proceeds by specifying a power dissipation value and an error value. An information error metric and a power metric is computed. Activation and deactivation of at least a portion of the first modul
Agazzi Oscar E.
Creigh John L.
Hatamian Mehdi
Samueli Henry
Broadcom Corporation
Liu Shuwang
McAndrews Held & Malloy Ltd.
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