Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-26
2003-02-18
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185080, C365S185110
Reexamination Certificate
active
06522586
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to non-volatile semiconductor memory and to methods for maintaining accurate storage of data in a non-volatile semiconductor memory.
2. Description of Related Art
A conventional non-volatile memory such as a Flash memory has memory cells that include floating gate transistors. Each floating gate transistor stores data as charge trapped on an isolated floating gate. The charge trapped on the floating gate transistor determines the threshold voltage of the floating gate transistor, and a data value can be written to or read from a memory cell by setting or determining the threshold voltage of the floating gate transistor in the memory cell. If the methods for setting and determining threshold voltages are sufficiently accurate and dependable, multiple bits of data can be stored in each memory cell.
Time-dependent and voltage-dependent charge leakage from or onto the floating gate of a memory cell can change the threshold voltage of the memory cell. Voltage-dependent usually leakage results from programming or other operations on neighboring memory cells. Time-dependent charge leakage generally depends on the temperature of a memory circuit but occurs even when the memory is not accessing (i.e., erasing, programming, or reading) any memory cells. Conventionally, retention of stored data requires minimizing the charge leakage to maintain the threshold voltages of memory cells that store data and/or tracking changes in the threshold voltages.
Tracking circuits can use reference cells that are subject to charge leakage that is similar to memory cells storing data, and a comparison of a memory cell and a reference cell can indicate a correct data value even if the threshold voltages have changed. Such tracking circuits can also track changes in measured threshold voltages that result from differences in operating parameters such as the supply voltage or temperature for the memory. However, tracking circuits cannot track changes in threshold voltage for every memory cell with complete accuracy. Accordingly, each data value corresponds to a range of threshold voltages, and that range must be made sufficiently wide to cover variations in the threshold voltages representing the same data value. Since the full usable range of threshold voltages of a memory cell is limited, having a wide range for each data value reduces the number of bits that can be stored per memory cell. Accordingly, methods and circuits are sought for maintaining threshold voltages within narrow windows to ensure data integrity over time.
SUMMARY
In accordance with the invention, a non-volatile memory has an on-chip “refresh” capability, that periodically reads and rewrites the content of all or a portion of a memory. More particularly, a refresh operation reads the content of each memory cell and writes the read value back into the same or a different location in the memory. The refresh operation is performed before the memory cells' threshold voltages have drifted to a level that could cause an error when read. Accordingly, the value read is the value originally written, and rewriting that value removes the effect of any threshold voltage drift that occurred prior to the refresh operation. The time interval between refresh operations can be determined according to: the storage density per cell, i.e., the number of bits stored per cell; the allowable budget for threshold voltage drift without causing error; and charge-loss and charge-gain characteristics of the memory cells (per reliability test results).
In an exemplary embodiment, the refresh operation can read and rewrite data without the need for any additional external components. For example, data read from one sector of non-volatile memory cells can be directly written into a previously-erased sector of non-volatile memory cells. Alternatively, data read from a sector is temporarily stored in an on-chip buffer, the sector is erased, and data is rewritten back into the same locations.
One embodiment of the invention is a non-volatile memory that includes: memory cells (typically arranged in multiple arrays); erase, write, and read circuitry; a refresh timer; and a memory management unit. In response to a signal from the refresh timer, as asserted by arbitration logic, the memory management unit directs the erase, write, and read circuitry to perform a refresh operation. In particular, the refresh operation includes reading data without generating a data signal for output from the non-volatile memory and writing the data to refresh threshold voltages of memory cells storing the data. An address mapping circuit can be used when the refresh operation moves data around within the memory. For example, before a refresh operation, the address mapping circuits converts a logical or virtual address corresponding to data to a first physical address. After the refresh operation, the address mapping circuits converts the virtual address signal corresponding to the data to a second physical address. The memory management unit optionally includes a data buffer that the memory management unit uses for data externally transferred and for the data read during the refresh operation for writing back into the memory cells.
Another embodiment of the invention is a method for operating a non-volatile memory. The method includes: storing data in the memory cells of the non-volatile memory, wherein each memory cell has a threshold voltage representing a multi-bit value; and periodically refreshing the threshold voltages representing the data by reading the data and rewriting the data. Periodically refreshing includes: determining a time since a last refresh operation; and performing a refresh operation if the time is greater than a predetermined refresh interval. The refresh interval is less than a ratio of a maximum tolerable drift for threshold voltages representing the data and an expected rate of drift of the threshold voltage.
In a non-volatile memory such as a Flash memory, a sector-based refresh operation includes: (a) selecting a sector that is designated as containing invalid data; (b) erasing the selected sector; (c) reading a following sector; (d) writing data from the following sector, to the selected sector; and (e) designating the following sector as containing invalid data. The following sector follows the selected sector in an ordering (e.g., a cyclic ordering) of sectors of the non-volatile memory. One or more repetition of steps (b), (c), and (d) uses as the selected sector for that repetition, the following sector last used. In a refresh of a single array, the read operations for memory cells in the following sector and write operations to memory cells in the selected sector are interleaved. When the selected and following sectors are in different arrays, reading, writing, and erasing can be performed in parallel. For example, reading from one array and simultaneously writing to another array. In one embodiment, for each repetition except a last of the repetitions, reading and writing for one repetition are simultaneous with erasing for a following repetition.
In another embodiment, a first repetition simultaneously erases the selected sector and reads data from the following sector into a buffer. The writing of data from the buffer to the selected sector is simultaneous with erasing the following sector for the next repetition. In that next repetition, reading data from the following sector and writing data to the select sector are simultaneous.
Another method for operating a non-volatile memory in accordance with an embodiment of the invention, includes: performing a first refresh operation that reads data from a first location having a first physical address in the non-volatile memory and writes the data to a second location having a second physical address in the memory; operating the memory using a first address mapping that maps a logical address corresponding to the data to the second physical address; performing a second refresh operation that reads the data from second locations in the non-vo
Le Vu A.
Millers David T.
Multi Level Memory Technology
Nguyen Van-Thu
LandOfFree
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