Dynamic ratioless circuitry for random logic applications

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307225C, 307443, 307482, H03K 19096, H03K 1920, H03K 19003, H03K 17687

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active

043161065

ABSTRACT:
A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase. A capacitor (38) is interconnected to the first node (A) and the output transistor (36) and is clocked by the second clock phase for maintaining the first node (A) at a predetermined voltage level by a bootstrapping operation.

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patent: 4114049 (1978-09-01), Suzuki
Landers, "MOS Shift Registers"; The Electric Engineer; pp. 59-61; 3/1970.
Penney et al., MOS/LSI Integrated Circuits; Van Nostrand Reinhold Company, 1972; pp. 260-288.
Carr et al., MOS/LSI Design and Application; McGraw-Hill; 1972; pp. 150-167.
Joynson et al., IEEE Journal of Solid-State Circuits; vol. SC-7, No. 3, pp. 217-224; 6/1972.
Knepper, IEEE Journal of Solid-State Circuits; vol. SC-13, No. 5; pp. 542-548; 10/1978.

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