Dynamic random access semiconductor memory wherein the RAS and C

Details Dynamic random access semiconductor memory wherein the RAS and C Dynamic random access semiconductor memory wherein the RAS and C

1987-11-09

1989-05-16

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365193, 365208, 365177, G11C 800, G11C 702, G11C 1134

Patent

active

048315974

ABSTRACT:
A dynamic random access semiconductor memory device includes a bit line pair to which at least one memory cell is connected, a bit line sense amplifier connected between the bit line pair and an input/output line pair, and a word line connected to the memory cell. The bit line sense amplifier includes a differential amplifier whose driving transistors are bipolar transistors. The bit line pair is selected at a first timing by a row address signal and the word line is selected at a second timing following the first timing by a column address signal.

REFERENCES:
patent: 4656613 (1987-04-01), Norwood et al.
patent: 4685089 (1987-08-01), Patet et al.

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