Dynamic random access memory with read-write signal of shortened

Details Dynamic random access memory with read-write signal of shortened Dynamic random access memory with read-write signal of shortened

1990-01-24

1992-01-07

Bowler, Alyssa H.

Static information storage and retrieval

Addressing

Sync/clocking

36518901, 36518905, 365203, G11C 700, G11C 11406, G11C 11413

Patent

active

050797484

ABSTRACT:
A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

REFERENCES:
patent: 4755964 (1988-07-01), Miner
patent: 4766572 (1988-08-01), Kobayashi
patent: 4794567 (1988-12-01), Akatsuka
patent: 4841488 (1989-06-01), Sanada
patent: 4945517 (1990-07-01), Miyatake et al.
IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, S. 929-933.

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