Dynamic random access memory wherein timing of completion of dat

Details Dynamic random access memory wherein timing of completion of dat Dynamic random access memory wherein timing of completion of dat

1995-04-19

1996-09-03

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

365149, 36518901, 365207, G11C 700

Patent

active

055530320

ABSTRACT:
A dynamic random access memory includes a capacitor in at least one memory cell each for storing one bit digital data as a terminal voltage, at least one bit line corresponding to at least one memory cell, a gate provided for each of the capacitors in the memory cells and which controls an electrical connection/disconnection between a terminal of the capacitor in the memory cell which stores the terminal voltage and the bit line corresponding to the memory cell, and at least one data bus line provided for at least one bit line. A current is continuously supplied to each of at least one of the data bus lines from a predetermined source through a predetermined resistor, and a reading voltage output unit provided for each of the bit lines, connects a current input terminal thereof with a data bus corresponding to the bit line, and changes a voltage of the data bus according to the voltage change on the bit line.

REFERENCES:
patent: 4947377 (1990-08-01), Hannai
patent: 4954992 (1990-09-01), Kimanoya et al.
patent: 4984206 (1991-01-01), Komatsu et al.
patent: 5051954 (1991-09-01), Toda et al.
patent: 5184326 (1993-02-01), Hoffmann et al.
Arimoto et al., "A Speed-Enhanced DRAM Array Architecture with Embedded ECC," IEEE Journal Of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, New York, NY, pp. 11-16.

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