Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2000-12-27
2001-10-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
Conservation of power
C365S226000, C365S205000, C365S233100
Reexamination Certificate
active
06307803
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89124359, filed Nov. 17, 2000.
BACKGROUND OF THIS INVENTION
1. Field of the Invention
This invention relates to a dynamic random access memory (DRAM) and a method for operating the same, and more particularly, to a structure and an operating method for a dynamic random access memory suitable for use as a compatible transistor of a static random access memory (SRAM). The dynamic random access memory is used as the compatible transistor of a static random access memory, that is, a static random access memory with a single transistor.
2. Description of Related Prior Art
A conventional dynamic random access memory comprises a transistor and a capacitor. The area and fabrication cost of the dynamic random access memory is much smaller than those of a static random access memory cell since the conventional static random access memory comprises 4 to 6 transistors. Therefore, to replace the static random access memory with the dynamic random access memory becomes a goal that the industry has endeavored to reach.
However, the data stored in the dynamic random access memory cell has to be refreshed periodically. Such operation is not required for the data stored in the static random access memory. The refresh operation of the dynamic random access memory cell wastes a significant bandwidth of the memory. For example, the clock time of a dynamic random access memory cell operated with a frequency of 100 MHz is 10 nsec. The time for storing a data externally is 10 nsec, and the refresh time is also 10 nsec. The actual refresh time can range from 16 to 500 nsec, depending on the specific circuit design and the capacity of the memory. Thus, the dynamic random access memory has to be idled once for every 500 nsec. The efficiency is consequently dropped to 50-90%. This consideration further reduces the bandwidth of operation.
In the prior art, an attempt for using the dynamic random access memory in the static random access memory has been made. Yet, the property of storing data for a long term has not been achieved since such dynamic random access memory requires an external signal to control the refresh operation. As a consequence, the static random access memory is delayed due to the refresh operation, so the dynamic random access memory is not compatible with the static random access memory.
In other prior art, a high speed static random access memory cache has been used together with a relatively low speed dynamic random access memory to increase the average access time for memory (U.S. Pat. No. 5,559,750). The actual access time for such a structure is dependent on the hit rate of the static random access memory cache, and an additional circuit is required to provide the refresh operation of the dynamic random access memory. Such a structure is still affected by the external access operation, so that a random access time for the integrated structure cannot be achieved.
In another structure, a dynamic random access memory with many memory cell rows is used to reduce the access time of the dynamic random access memory. However, this structure does not allow for the delay of one of the memory cell rows for refresh.
In U.S. Pat. No. 6,028,804, a static random access memory using a dynamic random access memory has been disclosed. An access arbiter is used to arbitrate between the clock required by external access and the generated refresh clock. The clock of the external access has priority in order to avoid a conflict, and it is inevitable that this structure will lose a portion of the operation frequency.
SUMMARY OF THIS INVENTION
This invention provides a structure and an operating method for a static random access memory using a dynamic random access memory. The data stored in the dynamic random access memory can be effectively retained without affecting the normal operation of the static random access memory.
The static random access memory can retain the data stored in the dynamic random access memory under a low voltage operational condition, and the power consumption for the operation can be effectively reduced.
In standby mode or sleep mode, the data stored in the dynamic random access memory can still be retained with a lower power consumption.
The dynamic random access memory suitable for use as a compatible transistor of a static random access memory is operated under a normal operation mode and a low voltage operation mode. Such dynamic random access memory structure uses a reference clock signal as the reference for operation. A memory cell is included to store a data. A sense amplifier comprising a sense unit, a first transistor and a second transistor is further included. The sense unit is coupled to the first transistor, the second transistor, a bit line and a complementary bit line. The bit line and the complementary bit line are used to access and refresh the data stored in the memory cell. The frequency for refreshing the data stored in the memory cell depends on the reference clock signal. The dynamic random access memory structure further comprises a switch to receive a first and a second voltage. Either one of the first and the second voltage is output as an operation voltage. The potential level of the first voltage is higher than the potential level of the second voltage. When the dynamic random access memory structure is operated under a normal operation mode, the second voltage is provided as the operation voltage for the dynamic random access memory. The power consumption for this operation can be reduced. When the dynamic random access memory is operated under the low voltage, the first voltage is the operation voltage to maintain data stored in the memory cell of the dynamic random access memory.
In the above dynamic random access memory structure, the memory cell comprises a third transistor and a capacitor. One terminal of the capacitor is connected to one source/drain of the third transistor, while the other terminal of the capacitor is connected to a third voltage. The other source/drain of the third transistor is coupled to the bit line. Under the normal operation mode, the third voltage is a proportion of the operation voltage, while the third voltage is smaller than the operation voltage. When the dynamic random access memory is operated under a low voltage mode, the third voltage drops to 0 voltage when the reference clock signal is at a low voltage of 0. The required voltage for maintaining the data stored in the memory cell of the dynamic random access memory is thus reduced.
The third transistor comprises a substrate coupled to a substrate bias which is provided by the reference clock signal.
The dynamic random access memory structure further comprises a voltage drop apparatus coupled to the first voltage of the switch and outputting the second voltage to the switch.
The invention further provides a dynamic random access memory structure suitable for use as a compatible transistor of a static random access memory. The dynamic random access memory structure is operated under one of either a normal operation mode, a stand-by mode or a sleep mode. A reference clock signal is used as a reference for operation. A memory cell is included by the dynamic random access memory for storing data, and a sense amplifier comprising a sense unit, a first transistor, a second transistor, a bit line and a complementary bit line is also included. The bit line and the complementary bit line are used to access and refresh the data stored in the memory cell. The frequency for refreshing the data stored in the memory cell depends on the reference clock signal. The dynamic random access memory structure further comprises a switch to receive a first and a second voltage and select one of them as the operation voltage. The first voltage has a potential level higher than the second voltage. When the dynamic random access memory is operated under a normal mode, the second voltage is the operation voltage to save the consumption power. When the dynamic random acce
Huang Jiawei
J. C. Patents
Lam David
Nelms David
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