Dynamic random access memory persistent page implemented as proc

Details Dynamic random access memory persistent page implemented as proc Dynamic random access memory persistent page implemented as proc

1995-05-25

1996-09-10

Nguyen, Viet Q.

Static information storage and retrieval

Powering

Conservation of power

365205, 365228, 365229, 36523001, G11C 700

Patent

active

055555284

ABSTRACT:
The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

REFERENCES:
patent: 5272677 (1993-12-01), Yamamura
patent: 5287320 (1994-02-01), Adachi
patent: 5463585 (1995-10-01), Sanada

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