Dynamic random access memory having small cycle time period

Details Dynamic random access memory having small cycle time period Dynamic random access memory having small cycle time period

1984-11-15

1986-04-08

Moffitt, James W.

Static information storage and retrieval

Addressing

G11C 800

Patent

active

045817227

ABSTRACT:
A dynamic random access memory wherein a memory access operation is started by receiving an address strobe signal (RAS, CAS), after which address signals (RA.sub.i, RA.sub.i, CA.sub.i, CA.sub.i) are applied via address buffers (2, 6) to address decoders (3', 7'). The address buffers (2, 6) and the NOR gates (31, 71) of the decoders (3', 7') are automatically reset earlier during the active operation, while the drivers (32, 72) of the decoders (3', 7') and their subsequent circuits are reset after the completion of the active period defined by the strobe signal.

REFERENCES:
patent: 4376989 (1983-03-01), Takemae
patent: 4396845 (1983-08-01), Nakano
patent: 4472792 (1984-09-01), Shimohigashi et al.
patent: 4509148 (1985-02-01), Asano et al.
IEEE International Solid-State Circuits Conference, "A 35ns 64K Static Column DRAM", by Baba et al., ISCC 83, Feb. 23, 1983, pp. 64-65.

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