Dynamic random access memory having improved layout and method o

Details Dynamic random access memory having improved layout and method o Dynamic random access memory having improved layout and method o

1994-12-30

1995-10-10

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 60, H01L 218242

Patent

active

054570646

ABSTRACT:
A dynamic random access memory having an improved layout capable of having a large storage capacity with a small memory cell area as well as preventing the occurrence of short-circuiting by an increase in the process margin, and a method of arranging memory cells of the same. Each active region includes a first diffusion region, a second diffusion region in common with an adjacent memory cell and a channel forming region located between the first and second diffusion regions. First diffusion regions of adjacent active regions are located at positions symmetrical with respect to the common second diffusion region, at a predetermined angle. Each of uniformly spaced bit lines has a protrusion having a predetermined width and length and extending from its one edge in a direction that the word lines extend. At the protrusion, one second diffusion region is disposed. Uniformly spaced word lines cross bit lines. Each capacitor is positioned between two adjacent bit lines and between two adjacent word lines. Each first contact hole is located on the center of each capacitor. Each bit line has a bent portion for preventing a short-circuiting caused by a contact with a protrusion of adjacent bit line. Each word line has a bent portion for preventing a short-circuiting caused by a contact with each corresponding first contact hole.

REFERENCES:
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5006481 (1991-04-01), Chan et al.
patent: 5014103 (1991-05-01), Ema
patent: 5045899 (1991-09-01), Arimoto
patent: 5155057 (1992-10-01), Dennison et al.
patent: 5227322 (1993-06-01), Ko et al.
patent: 5250831 (1993-10-01), Ishii
patent: 5375576 (1994-12-01), Kimura et al.
T. Ema et al., "3-Dimensional Stacked Capacitor Cell For 16M and 64M Drams", Dec. 11-14, 1988, pp. 592-599, IEDM 1988.
Shin'ichiro Kimura, et al., "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-Line Structure"; Dec. 11-14, 1988, pp. 596-599, IEDM 1988.

Affiliated with

Also associated with

Rating

Dynamic random access memory having improved layout and method o does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic random access memory having improved layout and method o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory having improved layout and method o will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2310170