Dynamic random access memory having buried word lines

Details Dynamic random access memory having buried word lines Dynamic random access memory having buried word lines

1988-02-16

1989-10-10

Hille, Rolf

357 55, 357 42, H01L 2978, H01L 2906, H01L 2702

Patent

active

048735604

ABSTRACT:
This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.

REFERENCES:
patent: 4476547 (1984-10-01), Miyasaka
patent: 4710789 (1987-12-01), Furutani et al.
patent: 4769786 (1988-09-01), Garnache et al.
Taguchi et al., "Dielectrically Encapsulated Trench Capacitor Cell", IEDM 86, pp. 136-139.
Kaga et al., "Half-V.sub.cc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring", IEEE Transactions on Electron Devices, vol. 35, No. 8, Aug. 1988, pp. 1257-1263.

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