Dynamic random access memory having a trench capacitor

Details Dynamic random access memory having a trench capacitor Dynamic random access memory having a trench capacitor

1986-12-08

1990-01-16

James, Andrew J.

Fishing, trapping, and vermin destroying

357 55, 437984, H01L 2978

Patent

active

048946966

ABSTRACT:
A very highly integrated semiconductor memory which enables the dynamic random access memory to develop less soft error and to eliminate margin for aligning the masks, that hinders the device from being highly integrated. The memory cell capacitor is constituted by a trench which is provided at a position defined by an insulator formed on the side of gate electrode of a MOS transistor that constitutes the memory cell. Therefore, the MOS transistor and the trench capacitor are self-aligned, and no margin is required for alignment.

REFERENCES:
patent: 4366613 (1983-01-01), Ogura
patent: 4397075 (1983-08-01), Fatula
patent: 4403394 (1983-09-01), Shepard
patent: 4672410 (1987-06-01), Miura et al.
patent: 4673962 (1987-06-01), Chatterjee
patent: 4683486 (1987-07-01), Chatterjee
patent: 4688063 (1987-08-01), Lu
patent: 4721987 (1988-01-01), Baglee et al.
patent: 4791463 (1988-12-01), Malhi
IBM Technical Disclosure Bulletin, vol. 26, #5, pp. 2597-2599, Oct. 1983, by Chao

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