Dynamic random access memory (DRAM) with cache and tag

Details Dynamic random access memory (DRAM) with cache and tag Dynamic random access memory (DRAM) with cache and tag

1994-08-29

1996-11-19

Swann, Tod R.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395432, 365 49, 36523003, G06F 1200

Patent

active

055772234

ABSTRACT:
A dynamic RAM having a TAG address holding circuit in a TAG block in correspondence with one of a plurality of sub-arrays to hold the lower bits of an X (row) address. A block control circuit in the TAG block determines a "Hit" or "Miss" in accordance with the held address and a new X address in response to the sub-address and outputs a TAG determination signal. In response to the TAG judgment signal, a sub-array control circuit transfers a signal for access to the TAG block and a column sense amplifier. The column sense amplifier is utilized as a cache and data latched in the column sense amplifier are read out on a data bus when a "Hit" is determined.

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