Dynamic random access memory device with sense amplifiers servin

Details Dynamic random access memory device with sense amplifiers servin Dynamic random access memory device with sense amplifiers servin

1994-08-17

1996-06-18

Zarabian, A.

Static information storage and retrieval

Addressing

Byte or page addressing

36523003, G11C 800

Patent

active

055285520

ABSTRACT:
A dynamic random access memory device causes sense amplifier circuits to serve as a cache memory for sequentially delivering data bits in the sense amplifier circuits, and a row address buffer unit is controlled independently of the sense amplifier circuits so as to change the row address signal without canceling the data bits in the sense amplifier circuits.

REFERENCES:
patent: 4480320 (1984-10-01), Naiff
patent: 4802135 (1989-01-01), Shinoda
patent: 4907203 (1990-03-01), Wada
patent: 5367495 (1994-11-01), Ishikawa
"Full Portrait of 4.5M Rambus DRAM-Realize 500 M-byte/second Date Transmission Speed through 72-bit Row Function", Kushiyama and Furyama, Aug. 1992, pp. 75-80.

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