Dynamic random access memory device having first and second I/O

Details Dynamic random access memory device having first and second I/O Dynamic random access memory device having first and second I/O

1994-06-21

1996-03-05

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

36518904, 36523006, G11C 700

Patent

active

054973490

ABSTRACT:
A dynamic random access memory device has a memory cell array which includes a first memory cell array part and a second memory cell array part portioned in a first direction parallel with the bit lines, a plurality of column switches, one provided for each of the bit lines, a plurality of input/output lines each connected to different ones of the bit lines via associated ones of the column switches, a row address decoder for decoding a first portion of an address signal and a column address decoder for decoding a second portion of the address signal to thereby simultaneously access at least two memory cells with the address signal. The input/output lines extend in a second direction parallel with word lines and are divided into first and second groups of input/output lines connected to those bit lines which belong to the first and second memory cell array parts, respectively in which the first input/output line group is isolated from the second input/output line group. A first input/output gate circuit is connected to the first group of input/output lines and a second input/output gate circuit is connected to the second group of input/output lines, in which the first and second input/output gate circuits serve to selectively transfer therethrough, between main amplifiers and the first input/output line groups, data to be simultaneously read from or written into the at least two memory cells in the memory cell array.

REFERENCES:
patent: 4916700 (1990-04-01), Ito et al.
patent: 4941129 (1990-07-01), Oshima et al.
patent: 4974373 (1990-08-01), Yamaguchi et al.
patent: 5029330 (1991-07-01), Kajigaya
patent: 5043947 (1991-08-01), Oshima et al.
patent: 5301142 (1994-04-01), Suzuki et al.
patent: 5317536 (1994-05-01), Aoyama
patent: 5369619 (1994-11-01), Ohba

Affiliated with

Also associated with

Rating

Dynamic random access memory device having first and second I/O does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic random access memory device having first and second I/O , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory device having first and second I/O will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1417073