Dynamic random access memory device having column selector for s

Details Dynamic random access memory device having column selector for s Dynamic random access memory device having column selector for s

1993-07-16

1994-11-29

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518901, 36518904, G11C 700, G11C 800

Patent

active

053696204

ABSTRACT:
A plurality of data line pairs incorporated in a dynamic random access memory device extend over circuit components in parallel to a bit line pairs, and propagate a data bit between a read/write amplifier circuit and a sense amplifier unit shared between two memory cell blocks, wherein a column selector selectively charges one of the plurality of data line pairs before propagating the data bit so that a concentrated column selecting system and the data line pairs over the circuit components make the random access memory device possible to be fabricated on a relatively small semiconductor chip.

REFERENCES:
patent: 4758990 (1988-07-01), Uchida
patent: 4878203 (1989-10-01), Arakawa
patent: 4926387 (1990-05-01), Madland
patent: 4939691 (1990-07-01), Mizukami et al.
patent: 5157631 (1992-10-01), Shimogawa
M. Taguchi et al., "A 40ns 64Mb DRAM with Current-Sensing Data-Bus Amplifier", ISSCC91, Session 6, High-Density DRAM, Paper TA 6.5, Feb. 14, 1991.
T. Mano et al., "Circuit Technologies for 16Mb DRAMs", 1987 IEEE International Solid-State Circuits Conference, ISSCC87, Feb. 25, 1987, pp. 22-23 and 324.

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