Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate
1993-04-14
2001-05-29
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Powering
Data preservation
C365S226000, C365S201000
Reexamination Certificate
active
06240037
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a dynamic random access memory device and, more particularly, to a dynamic random access memory device equipped with an internal booster circuit for driving sense amplifier circuits with boosted voltage.
DESCRIPTION OF THE RELATED ART
A computer system is progressively scaled down, and various portable personal computer units are commercially available for users. The portable personal computer units are usually equipped with a secondary or rechargeable battery unit, and is powered with the rechargeable battery unit at any place inside and outside of a house.
Dynamic random access memory devices are incorporated in the portable personal computer unit, and a one-transistor one-capacitor memory cell is typical of the dynamic random access memory cells. The integration density of the dynamic random access memory device is progressively increased, and, on the contrary, the accumulated capacitance of the one-transistor onecapacitor type memory cell is decreased. The small capacitance only produces small differential voltage on the associated bit line pair, and the small differential voltage decreases a margin of the exact circuit behavior of the associated sense amplifier circuit. For this reason, various new technologies have been developed and used in the dynamic random access memory devices.
FIG. 1
illustrate an essential part of a typical example of the dynamic random access memory device, and reference numerals
1
,
2
,
3
,
4
and
5
respectively designate a memory cell array, a precharging/ balancing circuit
2
, a sense amplifier circuit, a driver circuit associated with the sense amplifier circuit
3
and a row address decoder/word line driver unit
5
. Although
FIG. 1
shows only one memory cell MC, a plurality of memory cells fabricate the memory cell array
1
, and are arranged in rows and columns.
The memory cell MC is of the one-transistor and onecapacitor type, and is implemented by a series combination of an n-channel enhancement type switching transistor SW
1
and a storage capacitor CP
1
. A word line WL is coupled with the gate electrode of the n-channel enhancement type switching transistor SW
1
, and the word line WL is driven by the row address decoder/word line driver unit
5
. The drain node of the n-channel enhancement type switching transistor SW
1
is coupled with a bit line BLa paired with a bit line BLb, and the bit lines BLa and BLb form in combination a bit line pair BLP. While row address decoder/word line driver unit
5
drives the word line WL to high voltage level, the n-channel enhancement type switching transistor SW
1
turns on so as to couple the storage capacitor with the bit line BLa, and small differential voltage takes place between the bit lines BLa and BLb depending upon the amount of electric charges accumulated in the storage capacitor.
The precharging/ balancing circuit
2
comprises two n-channel enhancement type charging transistors SW
2
and SW
3
coupled in series between the bit lines BLa and BLb, and an n-channel enhancement type balancing transistor SW
4
coupled between the bit lines BLa and BLb. The common source node of the n-channel enhancement type charging transistors SW
2
and SW
3
is coupled with a source of positive voltage level, and a precharge control signal is supplied to the gate electrodes of the n-channel enhancement type charging transistors SW
2
and SW
3
and to the gate electrode of the n-channel enhancement type balancing transistor SW
4
. While the precharge control signal goes up to high voltage level, the n-channel enhancement type charging transistors SW
2
and SW
3
and the n-channel enhancement type balancing transistor SW
4
turn on, and the bit lines BLa and BLb are charged to a predetermined precharge level. The precharging is carried out before the row address decoder/word line driver unit
5
drives the word line WL, and the storage capacitor CP
1
slightly changes the voltage level on the bit line BLa so that the small differential voltage takes place between the bit lines BLa and BLb.
The sense amplifier circuit
3
is implemented by a flip flop circuit or two series combinations of p-channel enhancement type field effect transistors QP
1
and QP
2
and n-channel enhancement type field effect transistors QN
3
and QN
4
. The two series combinations are coupled between a high power supply line SAP and a lower power supply line SAN, and the common drain nodes DN
1
and DN
2
are respectively coupled with the bit lines BLa and BLb. The gate electrodes of the field effect transistors QP
1
and QN
3
are coupled with the drain node DN
2
, and the other drain node DN
1
is coupled with the gate electrodes of the field effect transistors QP
2
and QN
4
. When the sense amplifier circuit
3
is powered by the driver circuit
4
, the sense amplifier circuit
3
develops the small differential voltage between the bit lines BLa and BLb.
The driver circuit
4
comprises a p-channel enhancement type switching transistor SW
5
coupled between a positive power voltage line Vcc and the power supply line SAP, an n-channel enhancement type switching transistor SW
6
coupled between a ground voltage line and the other power supply line SAN, an inverter IV
1
and a balancing circuit
4
a
coupled between the power supply lines SAP and SAN, and the balancing circuit
4
a
has a series combination of n-channel enhancement type switching transistors SW
7
and SW
8
coupled between the power supply lines SAP and SAN and an n-channel enhancement type switching transistor SW
9
coupled in parallel to the series combination between the power supply lines SAP and SAN. An activation signal is directly supplied to the gate electrode of the n-channel enhancement type switching transistor SW
6
, and the inverter IV
1
supplies the complementary signal of the activation signal to the gate electrode of the p-channel enhancement type switching transistor SW
5
. The common source node of the n-channel enhancement type switching transistors SW
7
and SW
8
is coupled with a source of balance voltage level, and an inactivation signal is supplied to the gate electrodes of the n-channel enhancement type switching transistors SW
7
to SW
9
. While the bit line pair BLP stays at the precharging level, the inactivation signal allow the n-channel enhancement type switching transistors SW
7
to SW
9
to turn on, and the power supply line SAP is balanced with the power supply line SAN at the balance voltage level. For this reason, the sense amplifier circuit
3
is kept inactive, and any current does not flow through the sense amplifier circuit
3
. However, when the small differential voltage takes place between the bit lines BLa and BLb, the n-channel enhancement type switching transistors SW
7
to SW
9
turn off, and the activation signal and the complementary signal thereof allow the n-channel enhancement type switching transistor SW
6
and the p-channel enhancement type switching transistor SW
5
to turn on. Then, the power supply lines SAP and SAN are respectively conducted with the positive power supply line Vcc and the ground voltage line, and the positive power voltage Vcc and the ground voltage activates the sense amplifier circuit
3
for developing the small differential voltage.
Though not shown in
FIG. 1
, the differential voltage developed by the sense amplifier circuit is transferred to an output data buffer circuit, and the output data buffer circuit produces an output data signal indicative of a data bit stored in the memory cell MC from the differential voltage.
Thus, the electric charges accumulated in the storage capacitor is indicative of a data bit, and the data bit is propagated through the bit line pair BLP to the sense amplifier circuit
3
in the form of small differential voltage. Therefore, the amount of electric charges directly concerns the data propagation, and the voltage level on the bit line BLa is given by Equation 1.
Vx=
(
Cd×Vd+Cs×Vs
)/(
Cd+Cs
) Equation 1
where Cd is the parasitic capacitance coupled with t
Fears Terrell W.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas
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