Dynamic random access memory device having addressing section an

Details Dynamic random access memory device having addressing section an Dynamic random access memory device having addressing section an

1993-03-23

1994-08-23

Sikes, William L.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36523008, G11C 800

Patent

active

053413415

ABSTRACT:
A dynamic random access memory device is responsive to a row address signal and a column address signal supplied in synchronism with a system clock signal for providing a data path from a data input/output port and a memory cell selected from the memory cell array, and latch circuits are provided in the addressing section and the data transferring path for temporarily storing address decoded signal and write-in and read-out data bits in response to latch control signals higher in frequency than the system clock signal, thereby controlling the data stream in a pipeline fashion.

REFERENCES:
patent: 4986666 (1991-01-01), Homma
patent: 5086414 (1992-02-01), Nambu

Affiliated with

Also associated with

Rating

Dynamic random access memory device having addressing section an does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic random access memory device having addressing section an, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory device having addressing section an will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-507810