Dynamic random access memory device having a parallel testing mo

Details Dynamic random access memory device having a parallel testing mo Dynamic random access memory device having a parallel testing mo

1993-09-21

1995-07-25

Beausoliel, Jr., Robert W.

Excavating

371 212, 365201, G06F 1100

Patent

active

054369100

ABSTRACT:
A semiconductor random access memory device is subjected to a parallel testing operation to see whether or not a defective memory cell is incorporated in the semiconductor random access memory device; in the parallel testing operation, a test bit of logic "1" level is sequentially written into a first predetermined address of each of data storage blocks by changing a column address, then, a test bit of logic "0" level is written into a second predetermined address of each of the data storage blocks by changing the column address again, and the write-in operation is repeated so as to form a checker-like bit pattern in each data storage block; after the formation of the test pattern, the test bits are sequentially read out from the first predetermined address of the data storage blocks to a read and write data bus system to see whether or not any one of the test bits are inconsistent with the other test bits so that the parallel testing is carried out on various bit patterns.

REFERENCES:
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patent: 5222038 (1993-06-01), Tsuchida et al.
patent: 5233610 (1993-08-01), Nakayama et al.
patent: 5267212 (1993-11-01), Takashima
patent: 5272673 (1993-12-01), Sugibayashi
Yamada et al., "A 64Mbit DRAM with Merged Match-Line Test Architecture", Technical Report of Electronic Information Communication Society, vol. 90, No. 496, SDM90-199, Mar. 1991, pp. 27-33.

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