Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-04-17
2004-08-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230030, C365S189040
Reexamination Certificate
active
06778461
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor memories. More specifically, the invention relates to random access memory (RAM) devices, which are also known as volatile memory devices. Still more specifically, the invention relates to a dynamic random access memory device (DRAM) to be used as a static RAM (SRAM).
BACKGROUND OF THE INVENTION
Random access memories (RAMs) can be grouped in two broad categories: dynamic RAMs (DRAMs) and static RAMs (SRAMs). A DRAM is a memory device in which each memory cell comprises a small capacitor and a select transistor. The capacitor is used to store one of two prescribed values of electrical charges, representative of one bit of information, while the transistor is used to selectively allow access to the capacitor for reading or writing the stored information.
On the contrary, an SRAM is a memory device in which each memory cell comprises four or even six transistors and two resistors arranged to form a bistable circuit, i.e., a latch. The simpler structure of the DRAM memory cell as compared to the SRAM allows a very large array of memory cells to be integrated in a single semiconductor chip, and to achieve a larger storage capacity per unit chip area.
A drawback of DRAMs resides in the fact that since the information is stored in terms of an electrical charge of the memory cell capacitor, it is subjected to being lost, primarily due to the inevitable leakages of electrons across the semiconductor junctions. This makes it necessary to perform a periodic refresh operation of the information stored in each memory cell with a prescribed time period, so as to restore the prescribed electrical charge of the capacitor. SRAMs are not affected by this problem because of the latch structure of the memory cells thereof.
Several attempts have been made to make the DRAM refresh operation substantially transparent to the user. Several DRAM devices have also been proposed which do not require external signals to manage the refresh operation.
A common feature of the proposed DRAM devices is the provision of internal circuits adapted to generate the signals necessary to perform the refresh operation. These signals typically include the row address strobe (RAS) signal, the column address strobe (CAS) signal, the bit line pre-charge (PCH) signal and the sense (SEN) signal. In this way, the signals necessary to perform the refresh operation are not generated by a memory controller external to the memory device. Instead, they are generated by circuits internal to the memory device. DRAMs having this capability are therefore called self-refreshing. From the outside, a self-refreshing DRAM device can thus have the same number and kind of electrical terminals (pins) as an SRAM device of equal size.
The proposed self-refreshing DRAMs leave, however, the following problem unresolved. A feature of significant importance of an SRAM device is the certainty that the memory device provides a reply in a prescribed time to an external data request. In the proposed self-refreshing DRAMs the refresh procedure is hidden to the external user, but it is still performed internally to the memory device. It may thus happen that both the self-refreshing circuits internal to the memory device and the external user need to access a same memory word at the same time. The former for refreshing the information stored in the memory cells of the memory word, and the latter for reading or writing information from or to the memory word.
Additionally, due to the typical arrangement of the memory cells in a two-dimensional array, the above conflict occurs not only when the self-refreshing circuits and the external user need to access the very same memory word, but more generally when a simultaneous access to a same row of memory cells is required. A priority arbitration is thus necessary to establish which one of the two access requests has a higher priority. Normally, a higher priority is assigned to the external access request so that a suspension of the refresh operation becomes inevitable. If, as a consequence of repeated external access requests, the refresh operation is suspended too often, the data stored in some memory cells may get lost, since such memory cells are not refreshed within a prescribed time.
More recently, approaches have been proposed which implement write-back methods. According to these methods, the most recent accesses to the memory are performed on a back-up SRAM before being transferred to the array of DRAM memory cells. However, the internal architecture of the memory and the circuit complexity at least partially frustrate the advantage in terms of occupation of the chip area derived from using the small DRAM memory cell.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to provide a memory device functionally and structurally adapted to overcome the drawbacks of the prior art devices.
This and other objects, advantages and features according to the present invention are provided by a random access semiconductor memory comprising at least two memory banks, with each memory bank including a respective two-dimensional array of dynamic random access memory cells. Self-refresh circuits continuously submit the memory cells of the respective array to a refresh operation of data stored therein independently of the other memory bank.
The memory further includes first and second circuit means. The first circuit means are for selectively accessing one of the at least two memory banks in response to an external request of access to a memory location belonging to the memory bank. The second circuit means are for causing, in the accessed memory bank, a suspension of the refresh operation of the data stored in the memory cells of the respective array while serving the external request of access. The refresh operation is performed in the remaining memory bank.
Preferably, the first circuit means comprises a least significant bit of an external memory address, so that sequential access requests to contiguous memory locations in a memory address space causes sequential accesses to the memory banks. Advantageously, each of the memory banks comprises third circuit means for preventing the suspension of the refresh operation of the data stored in the memory cells of the respective array when a prescribed minimum period of the refresh operation is not respected. Preferably, the third circuit means causes the memory to generate an externally accessible alarm signal indicating that external access requests to the memory locations are suspended.
In one embodiment, the self-refresh circuits comprise a counter circuit for generating internal address signals for scanning the memory locations of the memory bank. The second circuit means comprise a count suspension circuit for suspending a count by the counter circuit.
The third circuit means may comprise a watch dog circuit operatively connected to the counter and re-triggered by the counter each time the counter circuit reaches a prescribed count value, for example, each time a counter overflow occurs. The watch dog circuit generates a memory bank alarm signal if two successive occurrences of the prescribed count, for example, two successive counter overflows, do not occur within a prescribed time with respect to the prescribed minimum period.
The watch dog circuit can comprise a re-triggerable monostable circuit. Preferably, the alarm signal is generated when at least one of the memory bank alarm signals is generated. The count suspension circuit can, for example, prevent a suspension of the count by the counter when the respective memory bank alarm signal is generated.
Advantageously, each memory bank comprises a row selection circuit for selecting a row of the respective two-dimensional array of memory cells according to a first group of bits of the external memory address, and a memory word selection circuit for selecting a memory word within the selected row according to a second group of bits of the external memory address. The first and second
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Nguyen Thinh T
STMicroelectronics S.r.l.
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