Static information storage and retrieval – Magnetic bubbles – One's and zero's
Reexamination Certificate
2007-10-23
2007-10-23
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Magnetic bubbles
One's and zero's
C365S189090, C365S230060
Reexamination Certificate
active
11412960
ABSTRACT:
A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
REFERENCES:
patent: 5566117 (1996-10-01), Okamura et al.
patent: 5636171 (1997-06-01), Yoo et al.
patent: 6483764 (2002-11-01), Chen Hsu et al.
patent: 6862239 (2005-03-01), Huang et al.
patent: 7027343 (2006-04-01), Sinha et al.
patent: 7177220 (2007-02-01), Chou et al.
S. Takase et al., 1.6-GByte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1600-1606, Nov. 1999.
Y. Idei et. al., Dual-Period Self-Refresh Scheme for Low-Power DRAM's with On-Chip PROM Mode Register, IEEE Journal of Solid-State Circuits, vol. 33, pp. 253-259, Feb. 1998.
Tsuruda et al., High-Speed/High-Bandwidth Design Methodologies for On-Chip DRAM Core Multimedia System LSI's, IEEE Journal of Solid-State Circuits, vol. 32, pp. 477-482, Mar. 1997.
Borden Ladner Gervais LLP
Hoang Huan
Hung Shin
Mosaid Technologies Incorporated
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