Dynamic random access memory device

Details Dynamic random access memory device Dynamic random access memory device

1982-06-25

1984-11-20

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365189, G11C 1140

Patent

active

044843127

ABSTRACT:
A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C.sub.00 .about.C.sub.127,127) in rows and columns and dummy cells (DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 ".about.DC.sub.2,127 ", DC.sub.20 "'.about.DC.sub.2,127 "') in rows. The capacitors (C.sub.d) of the dummy cells are charged to a high power supply potential (V.sub.CC) by one or more charging transistors (Q.sub.A or Q.sub.A ') clocked by a reset clock signal (.phi..sub.R). The capacitors (C.sub.d) of the dummy cells are discharged to a low power supply potential (V.sub.SS) by one or more transistors (Q.sub.B or Q.sub.B ') clocked by an operation clock signal (.phi..sub.WL) having a potential lower than the high power supply potential (V.sub.CC).

REFERENCES:
patent: 4419739 (1983-12-01), Blum
IEEE Journal of Solid-State Circuits, "A 64 kbit MOS Dynamic RAM with Novel Memory Capacitor", by Smith et al., vol. SC-15, No. 2, Apr. 1980, pp. 184-189.

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